linux-toradex.git/drivers/clocksource, branch v6.0-rc1 Linux kernel for Apalis and Colibri modules RISC-V: Add Sstc extension support 2022-08-11T21:41:52+00:00 Palmer Dabbelt palmer@rivosinc.com 2022-08-11T21:41:52+00:00 7ab52f75a9cf7fed7ba85802b986825dd72df641 This series implements Sstc extension support which was ratified recently. Before the Sstc extension, an SBI call is necessary to generate timer interrupts as only M-mode have access to the timecompare registers. Thus, there is significant latency to generate timer interrupts at kernel. For virtualized enviornments, its even worse as the KVM handles the SBI call and uses a software timer to emulate the timecomapre register. Sstc extension solves both these problems by defining a stimecmp/vstimecmp at supervisor (host/guest) level. It allows kernel to program a timer and recieve interrupt without supervisor execution enviornment (M-mode/HS mode) intervention. * palmer/riscv-sstc: RISC-V: Prefer sstc extension if available RISC-V: Enable sstc extension parsing from DT RISC-V: Add SSTC extension CSR details 
This series implements Sstc extension support which was ratified
recently.  Before the Sstc extension, an SBI call is necessary to
generate timer interrupts as only M-mode have access to the timecompare
registers. Thus, there is significant latency to generate timer
interrupts at kernel.  For virtualized enviornments, its even worse as
the KVM handles the SBI call and uses a software timer to emulate the
timecomapre register.

Sstc extension solves both these problems by defining a
stimecmp/vstimecmp at supervisor (host/guest) level. It allows kernel to
program a timer and recieve interrupt without supervisor execution
enviornment (M-mode/HS mode) intervention.

* palmer/riscv-sstc:
  RISC-V: Prefer sstc extension if available
  RISC-V: Enable sstc extension parsing from DT
  RISC-V: Add SSTC extension CSR details
RISC-V: Prefer sstc extension if available 2022-08-11T21:36:55+00:00 Atish Patra atishp@rivosinc.com 2022-07-22T16:50:46+00:00 9f7a8ff6391fd5363363b8e5c8b1462a07922368 RISC-V ISA has sstc extension which allows updating the next clock event via a CSR (stimecmp) instead of an SBI call. This should happen dynamically if sstc extension is available. Otherwise, it will fallback to SBI call to maintain backward compatibility. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/r/20220722165047.519994-4-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> 
RISC-V ISA has sstc extension which allows updating the next clock event
via a CSR (stimecmp) instead of an SBI call. This should happen dynamically
if sstc extension is available. Otherwise, it will fallback to SBI call
to maintain backward compatibility.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20220722165047.519994-4-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 2022-08-06T22:04:48+00:00 Linus Torvalds torvalds@linux-foundation.org 2022-08-06T22:04:48+00:00 4d1044fcb996e8de9b9ab392f4a767890e45202d Pull RISC-V updates from Palmer Dabbelt: - Enabling the FPU is now a static_key - Improvements to the Svpbmt support - CPU topology bindings for a handful of systems - Support for systems with 64-bit hart IDs - Many settings have been enabled in the defconfig, including both support for the StarFive systems and many of the Docker requirements There are also a handful of cleanups and improvements, as usual. * tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits) riscv: enable Docker requirements in defconfig riscv: convert the t-head pbmt errata to use the __nops macro riscv: introduce nops and __nops macros for NOP sequences RISC-V: Add fast call path of crash_kexec() riscv: mmap with PROT_WRITE but no PROT_READ is invalid riscv/efi_stub: Add 64bit boot-hartid support on RV64 riscv: cpu: Add 64bit hartid support on RV64 riscv: smp: Add 64bit hartid support on RV64 riscv: spinwait: Fix hartid variable type riscv: cpu_ops_sbi: Add 64bit hartid support on RV64 riscv: dts: sifive: "fix" pmic watchdog node name riscv: dts: canaan: Add k210 topology information riscv: dts: sifive: Add fu740 topology information riscv: dts: sifive: Add fu540 topology information riscv: dts: starfive: Add JH7100 CPU topology RISC-V: Add CONFIG_{NON,}PORTABLE riscv: config: enable SOC_STARFIVE in defconfig riscv: dts: microchip: Add mpfs' topology information riscv: Kconfig.socs: Add comments riscv: Kconfig.erratas: Add comments ... 
Pull RISC-V updates from Palmer Dabbelt:

 - Enabling the FPU is now a static_key

 - Improvements to the Svpbmt support

 - CPU topology bindings for a handful of systems

 - Support for systems with 64-bit hart IDs

 - Many settings have been enabled in the defconfig, including both
   support for the StarFive systems and many of the Docker requirements

There are also a handful of cleanups and improvements, as usual.

* tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits)
  riscv: enable Docker requirements in defconfig
  riscv: convert the t-head pbmt errata to use the __nops macro
  riscv: introduce nops and __nops macros for NOP sequences
  RISC-V: Add fast call path of crash_kexec()
  riscv: mmap with PROT_WRITE but no PROT_READ is invalid
  riscv/efi_stub: Add 64bit boot-hartid support on RV64
  riscv: cpu: Add 64bit hartid support on RV64
  riscv: smp: Add 64bit hartid support on RV64
  riscv: spinwait: Fix hartid variable type
  riscv: cpu_ops_sbi: Add 64bit hartid support on RV64
  riscv: dts: sifive: "fix" pmic watchdog node name
  riscv: dts: canaan: Add k210 topology information
  riscv: dts: sifive: Add fu740 topology information
  riscv: dts: sifive: Add fu540 topology information
  riscv: dts: starfive: Add JH7100 CPU topology
  RISC-V: Add CONFIG_{NON,}PORTABLE
  riscv: config: enable SOC_STARFIVE in defconfig
  riscv: dts: microchip: Add mpfs' topology information
  riscv: Kconfig.socs: Add comments
  riscv: Kconfig.erratas: Add comments
  ...
Merge tag 'timers-v5.20-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 2022-07-28T10:33:34+00:00 Thomas Gleixner tglx@linutronix.de 2022-07-28T10:33:34+00:00 75fed76ebc8f75e7a9f8c9ca39482aa34932ad41 Pull clockevent/source updates from Daniel Lezcano: - Add the missing DT bindings for the MTU nomadik timer (Linus Walleij) - Fix grammar typo in the ARM global timer Kconfig option (Randy Dunlap) - Add the tegra186 timer and use it on the tegra234 board (Thierry Reding) - Add the 'CPUXGPT' CPU timer for Mediatek MT6795 and implement a workaround to overcome an ATF bug where the timer is not correctly initialized (AngeloGioacchino Del Regno) - Rework the suspend/resume approach to enable the feature on the timer even it is not an active clock and fix a compilation warning (Claudiu Beznea) - Add the Add R-Car Gen4 timer support along with the DT bindings (Wolfram Sang) - Add compatible for ti,am654-timer to support AM6 SoC (Tony Lindgren) - Fix Kconfig option to put it back to 'bool' instead of 'tristate' for the tegra186 (Daniel Lezcano) - Sort 'family,type' DT bindings for the Renesas timers (Geert Uytterhoeven) - Add compatible 'allwinner,sun20i-d1-timer' for Allwinner D1 (Samuel Holland) - Remove unnecessary (void*) conversions for sun4i (XU pengfei) - Remove unnecessary (void*) conversions for sun5i (Li zeming) Link: https://lore.kernel.org/all/7472984e-f502-5f27-82bf-070127dd85a5@linaro.org 
Pull clockevent/source updates from Daniel Lezcano:

  - Add the missing DT bindings for the MTU nomadik timer (Linus
    Walleij)

  - Fix grammar typo in the ARM global timer Kconfig option (Randy
    Dunlap)

  - Add the tegra186 timer and use it on the tegra234 board (Thierry
    Reding)

  - Add the 'CPUXGPT' CPU timer for Mediatek MT6795 and implement a
    workaround to overcome an ATF bug where the timer is not correctly
    initialized (AngeloGioacchino Del Regno)

  - Rework the suspend/resume approach to enable the feature on the
    timer even it is not an active clock and fix a compilation warning
    (Claudiu Beznea)

  - Add the Add R-Car Gen4 timer support along with the DT bindings
    (Wolfram Sang)

  - Add compatible for ti,am654-timer to support AM6 SoC (Tony Lindgren)

  - Fix Kconfig option to put it back to 'bool' instead of 'tristate'
    for the tegra186 (Daniel Lezcano)

  - Sort 'family,type' DT bindings for the Renesas timers (Geert
    Uytterhoeven)

  - Add compatible 'allwinner,sun20i-d1-timer' for Allwinner D1 (Samuel
    Holland)

  - Remove unnecessary (void*) conversions for sun4i (XU pengfei)

  - Remove unnecessary (void*) conversions for sun5i (Li zeming)

Link: https://lore.kernel.org/all/7472984e-f502-5f27-82bf-070127dd85a5@linaro.org
clocksource/drivers/sun5i: Remove unnecessary (void*) conversions 2022-07-27T15:01:52+00:00 Li zeming zeming@nfschina.com 2022-07-27T08:37:51+00:00 148399c90e25bb5d1aa6f3e1dde25fec6f4005f2 Remove unnecessary void* type castings. Signed-off-by: Li zeming <zeming@nfschina.com> Link: https://lore.kernel.org/r/20220727083751.5540-1-zeming@nfschina.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
Remove unnecessary void* type castings.

Signed-off-by: Li zeming <zeming@nfschina.com>
Link: https://lore.kernel.org/r/20220727083751.5540-1-zeming@nfschina.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
clocksource/drivers/sun4i: Remove unnecessary (void*) conversions 2022-07-27T15:01:52+00:00 XU pengfei xupengfei@nfschina.com 2022-07-20T02:07:35+00:00 7a93d490900edcdbd3833d8bb9a01b23d8bb461e Remove unnecessary void* type casting. Signed-off-by: XU pengfei <xupengfei@nfschina.com> Link: https://lore.kernel.org/r/20220720020735.3771-1-xupengfei@nfschina.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
Remove unnecessary void* type casting.

Signed-off-by: XU pengfei <xupengfei@nfschina.com>
Link: https://lore.kernel.org/r/20220720020735.3771-1-xupengfei@nfschina.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
clocksource/drivers/tegra186: Put Kconfig option 'tristate' to 'bool' 2022-07-27T15:00:49+00:00 Daniel Lezcano daniel.lezcano@linaro.org 2022-07-18T21:36:57+00:00 110a25357584a2d2d9f50accb1e89455c54290b6 The clocksources are built-in, they are not modules. We don't know if the core time framework is ready for clockevents / clocksources as modules. Revert back this option to 'bool'. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20220718213657.1303538-1-daniel.lezcano@linaro.org 
The clocksources are built-in, they are not modules. We don't know if
the core time framework is ready for clockevents / clocksources as
modules.

Revert back this option to 'bool'.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20220718213657.1303538-1-daniel.lezcano@linaro.org
clocksource/drivers/timer-ti-dm: Make driver selection bool for TI K3 2022-07-27T15:00:48+00:00 Tony Lindgren tony@atomide.com 2022-05-23T15:14:48+00:00 775343f9fde99b4e5e6470f9d8afd519ee67dfa3 The clocksource drivers do not currently have loadable modules as pointed out by Daniel Lezcano <daniel.lezcano@linaro.org>. Let's reconsider this later on once timer removal discussion has been done, and set timer-ti-dm to bool for TI K3 SoC. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220523151448.23732-1-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
The clocksource drivers do not currently have loadable modules as
pointed out by Daniel Lezcano <daniel.lezcano@linaro.org>.

Let's reconsider this later on once timer removal discussion has been
done, and set timer-ti-dm to bool for TI K3 SoC.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220523151448.23732-1-tony@atomide.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
clocksource/drivers/timer-ti-dm: Add compatible for am6 SoCs 2022-07-27T15:00:48+00:00 Tony Lindgren tony@atomide.com 2022-04-08T10:17:15+00:00 4e3203610a889c72e96ddfc9e601b9349ef19c00 Add compatible for ti,am654-timer to support the timers. For example, am654 has four timers in the MCU domain and 12 timers in the MAIN domain. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220408101715.43697-4-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
Add compatible for ti,am654-timer to support the timers. For example, am654
has four timers in the MCU domain and 12 timers in the MAIN domain.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220408101715.43697-4-tony@atomide.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
clocksource/drivers/timer-ti-dm: Make timer selectable for ARCH_K3 2022-07-27T15:00:48+00:00 Tony Lindgren tony@atomide.com 2022-04-08T10:17:14+00:00 ab0bbef3ae0f6b5a3b60671cd0124d0fc4fc2567 Let's make timer-ti-dm selectable for ARCH_K3, and add a separate option for OMAP_DM_SYSTIMER as there should be no need for it on ARCH_K3. For older TI SoCs, we are already selecting OMAP_DM_TIMER in arch/arm/mach-omap*/Kconfig. For mach-omap2, we need to now also select OMAP_DM_SYSTIMER. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220408101715.43697-3-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
Let's make timer-ti-dm selectable for ARCH_K3, and add a separate option
for OMAP_DM_SYSTIMER as there should be no need for it on ARCH_K3.

For older TI SoCs, we are already selecting OMAP_DM_TIMER in
arch/arm/mach-omap*/Kconfig. For mach-omap2, we need to now also select
OMAP_DM_SYSTIMER.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220408101715.43697-3-tony@atomide.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>