linux-toradex.git/drivers/clocksource, branch v6.15-rc7 Linux kernel for Apalis and Colibri modules clocksource/i8253: Use raw_spinlock_irqsave() in clockevent_i8253_disable() 2025-05-05T13:34:49+00:00 Sebastian Andrzej Siewior bigeasy@linutronix.de 2025-04-04T13:31:16+00:00 94cff94634e506a4a44684bee1875d2dbf782722 On x86 during boot, clockevent_i8253_disable() can be invoked via x86_late_time_init -> hpet_time_init() -> pit_timer_init() which happens with enabled interrupts. If some of the old i8253 hardware is actually used then lockdep will notice that i8253_lock is used in hard interrupt context. This causes lockdep to complain because it observed the lock being acquired with interrupts enabled and in hard interrupt context. Make clockevent_i8253_disable() acquire the lock with raw_spinlock_irqsave() to cure this. [ tglx: Massage change log and use guard() ] Fixes: c8c4076723dac ("x86/timer: Skip PIT initialization on modern chipsets") Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20250404133116.p-XRWJXf@linutronix.de 
On x86 during boot, clockevent_i8253_disable() can be invoked via
x86_late_time_init -> hpet_time_init() -> pit_timer_init() which happens
with enabled interrupts.

If some of the old i8253 hardware is actually used then lockdep will notice
that i8253_lock is used in hard interrupt context. This causes lockdep to
complain because it observed the lock being acquired with interrupts
enabled and in hard interrupt context.

Make clockevent_i8253_disable() acquire the lock with
raw_spinlock_irqsave() to cure this.

[ tglx: Massage change log and use guard() ]

Fixes: c8c4076723dac ("x86/timer: Skip PIT initialization on modern chipsets")
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/all/20250404133116.p-XRWJXf@linutronix.de
Merge tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 2025-04-04T16:49:17+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-04-04T16:49:17+00:00 4a1d8ababde685a77fd4fd61e58f973cbdf29f8c Pull RISC-V updates from Palmer Dabbelt: - The sub-architecture selection Kconfig system has been cleaned up, the documentation has been improved, and various detections have been fixed - The vector-related extensions dependencies are now validated when parsing from device tree and in the DT bindings - Misaligned access probing can be overridden via a kernel command-line parameter, along with various fixes to misalign access handling - Support for relocatable !MMU kernels builds - Support for hpge pfnmaps, which should improve TLB utilization - Support for runtime constants, which improves the d_hash() performance - Support for bfloat16, Zicbom, Zaamo, Zalrsc, Zicntr, Zihpm - Various fixes, including: - We were missing a secondary mmu notifier call when flushing the tlb which is required for IOMMU - Fix ftrace panics by saving the registers as expected by ftrace - Fix a couple of stimecmp usage related to cpu hotplug - purgatory_start is now aligned as per the STVEC requirements - A fix for hugetlb when calculating the size of non-present PTEs * tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (65 commits) riscv: Add norvc after .option arch in runtime const riscv: Make sure toolchain supports zba before using zba instructions riscv/purgatory: 4B align purgatory_start riscv/kexec_file: Handle R_RISCV_64 in purgatory relocator selftests: riscv: fix v_exec_initval_nolibc.c riscv: Fix hugetlb retrieval of number of ptes in case of !present pte riscv: print hartid on bringup riscv: Add norvc after .option arch in runtime const riscv: Remove CONFIG_PAGE_OFFSET riscv: Support CONFIG_RELOCATABLE on riscv32 asm-generic: Always define Elf_Rel and Elf_Rela riscv: Support CONFIG_RELOCATABLE on NOMMU riscv: Allow NOMMU kernels to access all of RAM riscv: Remove duplicate CONFIG_PAGE_OFFSET definition RISC-V: errata: Use medany for relocatable builds dt-bindings: riscv: document vector crypto requirements dt-bindings: riscv: add vector sub-extension dependencies dt-bindings: riscv: d requires f RISC-V: add f & d extension validation checks RISC-V: add vector crypto extension validation checks ... 
Pull RISC-V updates from Palmer Dabbelt:

 - The sub-architecture selection Kconfig system has been cleaned up,
   the documentation has been improved, and various detections have been
   fixed

 - The vector-related extensions dependencies are now validated when
   parsing from device tree and in the DT bindings

 - Misaligned access probing can be overridden via a kernel command-line
   parameter, along with various fixes to misalign access handling

 - Support for relocatable !MMU kernels builds

 - Support for hpge pfnmaps, which should improve TLB utilization

 - Support for runtime constants, which improves the d_hash()
   performance

 - Support for bfloat16, Zicbom, Zaamo, Zalrsc, Zicntr, Zihpm

 - Various fixes, including:
      - We were missing a secondary mmu notifier call when flushing the
        tlb which is required for IOMMU
      - Fix ftrace panics by saving the registers as expected by ftrace
      - Fix a couple of stimecmp usage related to cpu hotplug
      - purgatory_start is now aligned as per the STVEC requirements
      - A fix for hugetlb when calculating the size of non-present PTEs

* tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (65 commits)
  riscv: Add norvc after .option arch in runtime const
  riscv: Make sure toolchain supports zba before using zba instructions
  riscv/purgatory: 4B align purgatory_start
  riscv/kexec_file: Handle R_RISCV_64 in purgatory relocator
  selftests: riscv: fix v_exec_initval_nolibc.c
  riscv: Fix hugetlb retrieval of number of ptes in case of !present pte
  riscv: print hartid on bringup
  riscv: Add norvc after .option arch in runtime const
  riscv: Remove CONFIG_PAGE_OFFSET
  riscv: Support CONFIG_RELOCATABLE on riscv32
  asm-generic: Always define Elf_Rel and Elf_Rela
  riscv: Support CONFIG_RELOCATABLE on NOMMU
  riscv: Allow NOMMU kernels to access all of RAM
  riscv: Remove duplicate CONFIG_PAGE_OFFSET definition
  RISC-V: errata: Use medany for relocatable builds
  dt-bindings: riscv: document vector crypto requirements
  dt-bindings: riscv: add vector sub-extension dependencies
  dt-bindings: riscv: d requires f
  RISC-V: add f & d extension validation checks
  RISC-V: add vector crypto extension validation checks
  ...
Merge tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 2025-03-29T19:47:09+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-03-29T19:47:09+00:00 1c83601b8ffc1b4ba8dc7f35151131707a8a5ae7 Pull MIPS updates from Thomas Bogendoerfer: - Add support for multi-cluster configuration - Add quirks for enabling multi-cluster mode on EyeQ6 - Add DTS clocks for ralink - Cleanup realtek DTS - Other cleanups and fixes * tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (35 commits) MIPS: config: omega2+, vocore2: enable CLK_MTMIPS arch: mips: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX MIPS: cm: Fix warning if MIPS_CM is disabled MIPS: Fix Macro name MIPS: ds1287: Match ds1287_set_base_clock() function types MIPS: cevt-ds1287: Add missing ds1287.h include MIPS: dec: Declare which_prom() as static MIPS: Loongson2ef: Replace deprecated strncpy() with strscpy() mips: dts: ralink: mt7628a: update system controller node and its consumers mips: dts: ralink: mt7620a: update system controller node and its consumers mips: dts: ralink: rt3883: update system controller node and its consumers mips: dts: ralink: rt3050: update system controller node and its consumers mips: dts: ralink: rt2880: update system controller node and its consumers dt-bindings: clock: add clock definitions for Ralink SoCs MIPS: Use arch specific syscall name match function mips: dts: realtek: Add restart to Cisco SG220-26P mips: dts: realtek: Add RTL838x SoC peripherals mips: dts: realtek: Replace uart clock property mips: dts: realtek: Correct uart interrupt-parent mips: dts: realtek: Add SoC IRQ node for RTL838x ... 
Pull MIPS updates from Thomas Bogendoerfer:

 - Add support for multi-cluster configuration

 - Add quirks for enabling multi-cluster mode on EyeQ6

 - Add DTS clocks for ralink

 - Cleanup realtek DTS

 - Other cleanups and fixes

* tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (35 commits)
  MIPS: config: omega2+, vocore2: enable CLK_MTMIPS
  arch: mips: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX
  MIPS: cm: Fix warning if MIPS_CM is disabled
  MIPS: Fix Macro name
  MIPS: ds1287: Match ds1287_set_base_clock() function types
  MIPS: cevt-ds1287: Add missing ds1287.h include
  MIPS: dec: Declare which_prom() as static
  MIPS: Loongson2ef: Replace deprecated strncpy() with strscpy()
  mips: dts: ralink: mt7628a: update system controller node and its consumers
  mips: dts: ralink: mt7620a: update system controller node and its consumers
  mips: dts: ralink: rt3883: update system controller node and its consumers
  mips: dts: ralink: rt3050: update system controller node and its consumers
  mips: dts: ralink: rt2880: update system controller node and its consumers
  dt-bindings: clock: add clock definitions for Ralink SoCs
  MIPS: Use arch specific syscall name match function
  mips: dts: realtek: Add restart to Cisco SG220-26P
  mips: dts: realtek: Add RTL838x SoC peripherals
  mips: dts: realtek: Replace uart clock property
  mips: dts: realtek: Correct uart interrupt-parent
  mips: dts: realtek: Add SoC IRQ node for RTL838x
  ...
Merge tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2025-03-26T20:30:27+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-03-26T20:30:27+00:00 1e1ba8d23dae91e6a9cfeb1236b02749e8a49ab3 Pull clocksource/event updates from Thomas Gleixner: - Add support for suspend/resume in the STM32 LP-Timer driver with a follow up fix, which uses the proper method to setup the timer as a optional wakeup source instead of trying to force it as mandatory wakeup source. - The usual device tree updates to enable new SoC models in existing drivers. - Trivial spelling, style and indentation fixes * tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dt-bindings: timer: Add SiFive CLINT2 clocksource/drivers/stm32-lptimer: Use wakeup capable instead of init wakeup clocksource/drivers/exynos_mct: Fixed a spelling error clocksource/drivers/stm32-lptimer: Add support for suspend / resume dt-bindings: timer: exynos4210-mct: add samsung,exynos2200-mct-peris compatible dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible dt-bindings: timer: Correct indentation and style in DTS example 
Pull clocksource/event updates from Thomas Gleixner:

  - Add support for suspend/resume in the STM32 LP-Timer driver with a
    follow up fix, which uses the proper method to setup the timer as a
    optional wakeup source instead of trying to force it as mandatory
    wakeup source.

  - The usual device tree updates to enable new SoC models in existing
    drivers.

  - Trivial spelling, style and indentation fixes

* tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  dt-bindings: timer: Add SiFive CLINT2
  clocksource/drivers/stm32-lptimer: Use wakeup capable instead of init wakeup
  clocksource/drivers/exynos_mct: Fixed a spelling error
  clocksource/drivers/stm32-lptimer: Add support for suspend / resume
  dt-bindings: timer: exynos4210-mct: add samsung,exynos2200-mct-peris compatible
  dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible
  dt-bindings: timer: Correct indentation and style in DTS example
Merge tag 'hyperv-next-signed-20250324' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux 2025-03-25T21:47:04+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-03-25T21:47:04+00:00 a5b3d8660b049779880c790549ff3fef02f6922c Pull hyperv updates from Wei Liu: - Add support for running as the root partition in Hyper-V (Microsoft Hypervisor) by exposing /dev/mshv (Nuno and various people) - Add support for CPU offlining in Hyper-V (Hamza Mahfooz) - Misc fixes and cleanups (Roman Kisel, Tianyu Lan, Wei Liu, Michael Kelley, Thorsten Blum) * tag 'hyperv-next-signed-20250324' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: (24 commits) x86/hyperv: fix an indentation issue in mshyperv.h x86/hyperv: Add comments about hv_vpset and var size hypercall input args Drivers: hv: Introduce mshv_root module to expose /dev/mshv to VMMs hyperv: Add definitions for root partition driver to hv headers x86: hyperv: Add mshv_handler() irq handler and setup function Drivers: hv: Introduce per-cpu event ring tail Drivers: hv: Export some functions for use by root partition module acpi: numa: Export node_to_pxm() hyperv: Introduce hv_recommend_using_aeoi() arm64/hyperv: Add some missing functions to arm64 x86/mshyperv: Add support for extended Hyper-V features hyperv: Log hypercall status codes as strings x86/hyperv: Fix check of return value from snp_set_vmsa() x86/hyperv: Add VTL mode callback for restarting the system x86/hyperv: Add VTL mode emergency restart callback hyperv: Remove unused union and structs hyperv: Add CONFIG_MSHV_ROOT to gate root partition support hyperv: Change hv_root_partition into a function hyperv: Convert hypercall statuses to linux error codes drivers/hv: add CPU offlining support ... 
Pull hyperv updates from Wei Liu:

 - Add support for running as the root partition in Hyper-V (Microsoft
   Hypervisor) by exposing /dev/mshv (Nuno and various people)

 - Add support for CPU offlining in Hyper-V (Hamza Mahfooz)

 - Misc fixes and cleanups (Roman Kisel, Tianyu Lan, Wei Liu, Michael
   Kelley, Thorsten Blum)

* tag 'hyperv-next-signed-20250324' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: (24 commits)
  x86/hyperv: fix an indentation issue in mshyperv.h
  x86/hyperv: Add comments about hv_vpset and var size hypercall input args
  Drivers: hv: Introduce mshv_root module to expose /dev/mshv to VMMs
  hyperv: Add definitions for root partition driver to hv headers
  x86: hyperv: Add mshv_handler() irq handler and setup function
  Drivers: hv: Introduce per-cpu event ring tail
  Drivers: hv: Export some functions for use by root partition module
  acpi: numa: Export node_to_pxm()
  hyperv: Introduce hv_recommend_using_aeoi()
  arm64/hyperv: Add some missing functions to arm64
  x86/mshyperv: Add support for extended Hyper-V features
  hyperv: Log hypercall status codes as strings
  x86/hyperv: Fix check of return value from snp_set_vmsa()
  x86/hyperv: Add VTL mode callback for restarting the system
  x86/hyperv: Add VTL mode emergency restart callback
  hyperv: Remove unused union and structs
  hyperv: Add CONFIG_MSHV_ROOT to gate root partition support
  hyperv: Change hv_root_partition into a function
  hyperv: Convert hypercall statuses to linux error codes
  drivers/hv: add CPU offlining support
  ...
Merge branch 'kvm-arm64/pv-cpuid' into kvmarm/next 2025-03-19T21:53:16+00:00 Oliver Upton oliver.upton@linux.dev 2025-03-19T21:53:09+00:00 d300b0168ea8fd5022a1413bd37ab63f4e5a7d4d * kvm-arm64/pv-cpuid: : Paravirtualized implementation ID, courtesy of Shameer Kolothum : : Big-little has historically been a pain in the ass to virtualize. The : implementation ID (MIDR, REVIDR, AIDR) of a vCPU can change at the whim : of vCPU scheduling. This can be particularly annoying when the guest : needs to know the underlying implementation to mitigate errata. : : "Hyperscalers" face a similar scheduling problem, where VMs may freely : migrate between hosts in a pool of heterogenous hardware. And yes, our : server-class friends are equally riddled with errata too. : : In absence of an architected solution to this wart on the ecosystem, : introduce support for paravirtualizing the implementation exposed : to a VM, allowing the VMM to describe the pool of implementations that a : VM may be exposed to due to scheduling/migration. : : Userspace is expected to intercept and handle these hypercalls using the : SMCCC filter UAPI, should it choose to do so. smccc: kvm_guest: Fix kernel builds for 32 bit arm KVM: selftests: Add test for KVM_REG_ARM_VENDOR_HYP_BMAP_2 smccc/kvm_guest: Enable errata based on implementation CPUs arm64: Make  _midr_in_range_list() an exported function KVM: arm64: Introduce KVM_REG_ARM_VENDOR_HYP_BMAP_2 KVM: arm64: Specify hypercall ABI for retrieving target implementations arm64: Modify _midr_range() functions to read MIDR/REVIDR internally Signed-off-by: Oliver Upton <oliver.upton@linux.dev> 
* kvm-arm64/pv-cpuid:
  : Paravirtualized implementation ID, courtesy of Shameer Kolothum
  :
  : Big-little has historically been a pain in the ass to virtualize. The
  : implementation ID (MIDR, REVIDR, AIDR) of a vCPU can change at the whim
  : of vCPU scheduling. This can be particularly annoying when the guest
  : needs to know the underlying implementation to mitigate errata.
  :
  : "Hyperscalers" face a similar scheduling problem, where VMs may freely
  : migrate between hosts in a pool of heterogenous hardware. And yes, our
  : server-class friends are equally riddled with errata too.
  :
  : In absence of an architected solution to this wart on the ecosystem,
  : introduce support for paravirtualizing the implementation exposed
  : to a VM, allowing the VMM to describe the pool of implementations that a
  : VM may be exposed to due to scheduling/migration.
  :
  : Userspace is expected to intercept and handle these hypercalls using the
  : SMCCC filter UAPI, should it choose to do so.
  smccc: kvm_guest: Fix kernel builds for 32 bit arm
  KVM: selftests: Add test for KVM_REG_ARM_VENDOR_HYP_BMAP_2
  smccc/kvm_guest: Enable errata based on implementation CPUs
  arm64: Make  _midr_in_range_list() an exported function
  KVM: arm64: Introduce KVM_REG_ARM_VENDOR_HYP_BMAP_2
  KVM: arm64: Specify hypercall ABI for retrieving target implementations
  arm64: Modify _midr_range() functions to read MIDR/REVIDR internally

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Merge patch series "Support SSTC while PM operations" 2025-03-18T12:59:08+00:00 Alexandre Ghiti alexghiti@rivosinc.com 2025-03-18T12:59:08+00:00 a5edc510da314af336d1df133370a0608864e092 Nick Hu <nick.hu@sifive.com> says: When the cpu is going to be hotplug, stop the stimecmp to prevent pending interrupt. When the cpu is going to be suspended, save the stimecmp before entering the suspend state and restore it in the resume path. * patches from https://lore.kernel.org/r/20250219114135.27764-1-nick.hu@sifive.com: clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug riscv: Add stimecmp save and restore Link: https://lore.kernel.org/r/20250219114135.27764-1-nick.hu@sifive.com Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> 
Nick Hu <nick.hu@sifive.com> says:

When the cpu is going to be hotplug, stop the stimecmp to prevent pending
interrupt.
When the cpu is going to be suspended, save the stimecmp before entering
the suspend state and restore it in the resume path.

* patches from https://lore.kernel.org/r/20250219114135.27764-1-nick.hu@sifive.com:
  clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug
  riscv: Add stimecmp save and restore

Link: https://lore.kernel.org/r/20250219114135.27764-1-nick.hu@sifive.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug 2025-03-18T12:59:03+00:00 Nick Hu nick.hu@sifive.com 2025-02-19T11:41:35+00:00 70c93b026ed07078e933583591aa9ca6701cd9da Stop the timer when the cpu is going to be offline otherwise the timer interrupt may be pending while performing power-down. Suggested-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20250219114135.27764-3-nick.hu@sifive.com Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> 
Stop the timer when the cpu is going to be offline otherwise the
timer interrupt may be pending while performing power-down.

Suggested-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20250219114135.27764-3-nick.hu@sifive.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
clocksource/drivers/stm32-lptimer: Use wakeup capable instead of init wakeup 2025-03-07T16:55:59+00:00 Alexandre Torgue alexandre.torgue@foss.st.com 2025-03-06T10:25:01+00:00 96bf4b89a6ab22426ad83ef76e66c72a5a8daca0 "wakeup-source" property describes a device which has wakeup capability but should not force this device as a wakeup source. Fixes: 48b41c5e2de6 ("clocksource: Add Low Power STM32 timers driver") Cc: stable@vger.kernel.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Rule: add Link: https://lore.kernel.org/stable/20250306083407.2374894-1-fabrice.gasnier%40foss.st.com Link: https://lore.kernel.org/r/20250306102501.2980153-1-fabrice.gasnier@foss.st.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
"wakeup-source" property describes a device which has wakeup capability
but should not force this device as a wakeup source.

Fixes: 48b41c5e2de6 ("clocksource: Add Low Power STM32 timers driver")
Cc: stable@vger.kernel.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Rule: add
Link: https://lore.kernel.org/stable/20250306083407.2374894-1-fabrice.gasnier%40foss.st.com
Link: https://lore.kernel.org/r/20250306102501.2980153-1-fabrice.gasnier@foss.st.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
clocksource/drivers/exynos_mct: Fixed a spelling error 2025-03-07T16:55:59+00:00 Anindya Sundar Gayen anindya.sg@samsung.com 2025-02-28T13:11:38+00:00 7e1e4e62656fcf8fb05c0c39c649b16d78d7c8dc Fixed a spelling issue in driver /s/processer/processor/ Signed-off-by: Anindya Sundar Gayen <anindya.sg@samsung.com> Link: https://lore.kernel.org/r/20250228131138.9208-1-anindya.sg@samsung.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 
Fixed a spelling issue in driver /s/processer/processor/

Signed-off-by: Anindya Sundar Gayen <anindya.sg@samsung.com>
Link: https://lore.kernel.org/r/20250228131138.9208-1-anindya.sg@samsung.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>