linux-toradex.git/drivers/dma/hsu, branch v4.17

serial: 8250_mid: handle interrupt correctly in DMA case

2017-01-19T13:20:23+00:00

Starting from Tangier B0 and continuing on Anniedale the HSU DMA interrupt
line is actually shared with UART. Handling them independently is racy and
quite often comes with the following traceback.

 irq 54: nobody cared (try booting with the "irqpoll" option)
 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.9.0-rc6-edison64-86244934+ #1
 Hardware name: Intel Corporation Merrifield/BODEGA BAY, BIOS 542 2015.01.21:18.19.48
  ffff88003f203eb0 ffffffff8130e718 ffff880032627000 ffff88003262709c
  ffff88003f203ed8 ffffffff810a3960 ffff880032627000 0000000000000000
  ffff880032627000 ffff88003f203f10 ffffffff810a3cc7 ffff880032627000
 Call Trace:
  
  [] dump_stack+0x4d/0x65
  [] __report_bad_irq+0x30/0xc0
  [] note_interrupt+0x227/0x270
  [] handle_irq_event_percpu+0x40/0x50
  [] handle_irq_event+0x27/0x50
  [] handle_fasteoi_irq+0x85/0x150
  [] handle_irq+0x6e/0x120
  [] ? _local_bh_enable+0x1c/0x50
  [] do_IRQ+0x46/0xd0
  [] common_interrupt+0x7f/0x7f
  
  [] ? mwait_idle+0x7d/0x140
  [] arch_cpu_idle+0xa/0x10
  [] default_idle_call+0x20/0x30
  [] cpu_startup_entry+0x16d/0x1d0
  [] rest_init+0x6d/0x70
  [] start_kernel+0x3e2/0x3ef
  [] x86_64_start_reservations+0x38/0x3a
  [] x86_64_start_kernel+0xea/0xed
 handlers:
 [] serial8250_interrupt
 Disabling IRQ #54

Fix this by handling interrupt only in one place.

The issue is discussed here: https://github.com/andy-shev/linux/issues/5

Moreover this also fixes another bug when Rx DMA returns wrong residue and we
can't rely on it.

Reviewed-by: Heikki Krogerus 
Signed-off-by: Andy Shevchenko 
Acked-by: Vinod Koul 
Signed-off-by: Greg Kroah-Hartman

dmaengine: hsu: pci: switch to new API for IRQ allocation

2016-11-25T05:41:08+00:00

There is new API in place which provides allocation mechanism of interrupts for
PCI devices. Use it in the HSU DMA driver.

Signed-off-by: Andy Shevchenko 
Signed-off-by: Vinod Koul

dmaengine: hsu: refactor hsu_dma_do_irq() to return int

2016-09-02T13:05:48+00:00

Since we have nice macro IRQ_RETVAL() we would use it to convert a flag of
handled interrupt from int to irqreturn_t.

The rationale of doing this is:
a) hence we implicitly mark hsu_dma_do_irq() as an auxiliary function that
   can't be used as interrupt handler directly, and
b) to be in align with serial driver which is using serial8250_handle_irq()
   that returns plain int by design.

Signed-off-by: Andy Shevchenko 
Signed-off-by: Greg Kroah-Hartman

dmaengine: hsu: Export hsu_dma_get_status()

2016-06-25T21:30:42+00:00

To allow other code to safely read DMA Channel Status Register (where
the register attribute for Channel Error, Descriptor Time Out &
Descriptor Done fields are read-clear), export hsu_dma_get_status().
hsu_dma_irq() is renamed to hsu_dma_do_irq() and requires Status
Register value to be passed in.

Signed-off-by: Chuah, Kim Tatt 
Acked-by: Andy Shevchenko 
Reviewed-by: Heikki Krogerus 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma

2016-05-19T18:47:18+00:00

Pull dmaengine updates from Vinod Koul:
 "This time round the update brings in following changes:

   - new tegra driver for ADMA device

   - support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI
     Central Direct Memory Access Engine and few updates to this driver

   - new cyclic capability to sun6i and few updates

   - slave-sg support in bcm2835

   - updates to many drivers like designware, hsu, mv_xor, pxa, edma,
     qcom_hidma & bam"

* tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (84 commits)
  dmaengine: ioatdma: disable relaxed ordering for ioatdma
  dmaengine: of_dma: approximate an average distribution
  dmaengine: core: Use IS_ENABLED() instead of checking for built-in or module
  dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error event
  dmaengine: qcom_hidma: add support for object hierarchy
  dmaengine: qcom_hidma: add debugfs hooks
  dmaengine: qcom_hidma: implement lower level hardware interface
  dmaengine: vdma: Add clock support
  Documentation: DT: vdma: Add clock support for dmas
  dmaengine: vdma: Add config structure to differentiate dmas
  MAINTAINERS: Update Tegra DMA maintainers
  dmaengine: tegra-adma: Add support for Tegra210 ADMA
  Documentation: DT: Add binding documentation for NVIDIA ADMA
  dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine
  Documentation: DT: vdma: update binding doc for AXI CDMA
  dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine
  Documentation: DT: vdma: update binding doc for AXI DMA
  dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma
  dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLIC
  dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC
  ...

dmaengine: hsu: set maximum allowed segment size for DMA

2016-04-04T16:42:00+00:00

This tells, for example, IOMMU what the maximum size of a segment
the DMA controller can send.

Signed-off-by: Andy Shevchenko 
Signed-off-by: Vinod Koul

dmaengine: hsu: don't check direction of timeouted channel

2016-04-04T16:42:00+00:00

The timeout capability is only available on the so called DMA write channels,
i.e. associated with UART Rx FIFO. It means we don't need to check the
direction of the channel to handle timeouts.

Signed-off-by: Andy Shevchenko 
Signed-off-by: Vinod Koul

dmaengine: hsu: allow more than 3 descriptors

2016-04-04T16:42:00+00:00

Current code allows only up to 3 descriptors to be programmed to the hardware
since it is used wrong calculations. Change % to min_t() to allow as many
descriptors as user supplied. At once it could be programmed up to 4
descriptors due to hardware limitations.

The issue was found under stress test, so it might not bother ordinary users.

Signed-off-by: Andy Shevchenko 
Signed-off-by: Vinod Koul

dmaengine: hsu: correct use of channel status register

2016-04-04T16:41:43+00:00

There is a typo in documentation regarding to descriptor empty bit (DESCE)
which is set to 1 when descriptor is empty. Thus, status register at the end of
a transfer usually returns all DESCE bits set and thus it will never be zero.

Moreover, there are 2 bits (CDESC) that encode current descriptor, on which
interrupt has been asserted. In case when we have few descriptors programmed we
might have non-zero value.

Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when
reading it.

Fixes: 2b49e0c56741 ("dmaengine: append hsu DMA driver")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Shevchenko 
Signed-off-by: Vinod Koul

dmaengine: hsu: correct residue calculation of active descriptor

2016-04-04T16:41:43+00:00

The commit f0579c8ceaf1 ("dmaengine: hsu: speed up residue calculation")
speeded up calculation of the queued descriptor but broke the initial residue
value for active descriptor.

In accordance with documentation the hardware descriptor is updated each time
DMA transfered some bytes. It means we have to calculate a sum of lengths of
non-submitted hardware descriptors and whatever current values in the hardware.
Do this straightforward.

Fixes: f0579c8ceaf1 ("dmaengine: hsu: speed up residue calculation")
Cc: stable@vger.kernel.org
Signed-off-by: Andy Shevchenko 
Signed-off-by: Vinod Koul