linux-toradex.git/drivers/dma/mv_xor.h, branch v4.9.43

dmaengine: mv_xor: Add support for IO (PCIe) src/dst areas

2016-09-15T15:43:59+00:00

To enable the access to a specific area, the MVEBU XOR controllers needs
to have this area enabled / mapped via an address window. Right now,
only the DRAM memory area is enabled via such memory windows. So
using this driver to DMA to / from a e.g. PCIe memory region is
currently not supported.

This patch now adds support for such PCIe / IO regions by checking
if the src / dst address is located in an IO memory area in contrast
to being located in DRAM. This is done by using the newly introduced
MBus function mvebu_mbus_get_io_win_info(). If the src / dst address
is located in such an IO area, a new address window is created in
the XOR DMA controller. Enabling the controller to access this area.

Signed-off-by: Stefan Roese 
Cc: Gregory CLEMENT 
Cc: Thomas Petazzoni 
Cc: Marcin Wojtas 
Cc: Arnd Bergmann 
Cc: Andrew Lunn 
Cc: Vinod Koul 
Signed-off-by: Vinod Koul

dmaengine: mv_xor: use SoC type instead of directly the operation mode

2016-05-03T06:57:47+00:00

Currently the main difference between legacy XOR engine and newer one, is
the way the engine modes are setup (either in the descriptor or through
the controller registers). In order to be able to take into account new
generation of the XOR engine for the ARM64 SoC, we need to identify them
by type, and then depending to the type the engine setup will be
selected.

Signed-off-by: Gregory CLEMENT 
Signed-off-by: Vinod Koul

dmaengine: mv_xor: add suspend/resume support

2016-01-06T10:12:27+00:00

This commit adds suspend/resume support to the mv_xor driver. The
config and interrupt mask registers must be saved and restored, and
upon resume, the MBus windows configuration must also be done again.

Tested on Armada 388 GP, with a RAID 5 array, accessed before and
after a suspend to RAM cycle.

Based on work from Ofer Heifetz and Lior Amsalem.

Signed-off-by: Thomas Petazzoni 
Signed-off-by: Vinod Koul

dmaengine: mv_xor: remove mv_xor_chan->current_type field

2016-01-06T10:12:26+00:00

Since commit 3e4f52e2da9f6 ("dma: mv_xor: Simplify the DMA_MEMCPY
operation"), this field is no longer used, so get rid of it.

Signed-off-by: Thomas Petazzoni 
Reviewed-by: Maxime Ripard 
Signed-off-by: Vinod Koul

dmaengine: mv_xor: improve descriptors list handling and reduce locking

2015-06-10T16:48:31+00:00

This patch change the way free descriptors are marked.

Instead of having a field for descriptor in use, all the descriptors in the
all_slots list are free for use.

This simplify the allocation method and reduce the locking needed.

Signed-off-by: Lior Amsalem 
Reviewed-by: Ofer Heifetz 
Signed-off-by: Maxime Ripard 
Signed-off-by: Vinod Koul

dmaengine: mv_xor: Enlarge descriptor pool size

2015-06-10T16:48:31+00:00

Now that we have 2 channels assigned to 2 CPUs and all requests are chained
on same channels, we need much more descriptors available to satisfy
async_tx workload.

3072 descriptors was found in our lab as the number of descriptors which
allow the async_tx stack to work without waiting for free descriptors on
submission of new requests.

Signed-off-by: Lior Amsalem 
Reviewed-by: Nadav Haklai 
Tested-by: Nadav Haklai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Vinod Koul

dmaengine: mv_xor: add support for a38x command in descriptor mode

2015-06-10T16:48:30+00:00

The Marvell Armada 38x SoC introduce new features to the XOR engine,
especially the fact that the engine mode (MEMCPY/XOR/PQ/etc) can be part of
the descriptor and not set through the controller registers.

This new feature allows mixing of different commands (even PQ) on the same
channel/chain without the need to stop the engine to reconfigure the engine
mode.

Refactor the driver to be able to use that new feature on the Armada 38x,
while keeping the old behaviour on the older SoCs.

Signed-off-by: Lior Amsalem 
Reviewed-by: Ofer Heifetz 
Signed-off-by: Maxime Ripard 
Signed-off-by: Vinod Koul

dmaengine: mv_xor: bug fix for racing condition in descriptors cleanup

2015-06-10T16:48:30+00:00

This patch fixes a bug in the XOR driver where the cleanup function can be
called and free descriptors that never been processed by the engine (which
result in data errors).

The cleanup function will free descriptors based on the ownership bit in
the descriptors.

Fixes: ff7b04796d98 ("dmaengine: DMA engine driver for Marvell XOR engine")
Signed-off-by: Lior Amsalem 
Signed-off-by: Maxime Ripard 
Reviewed-by: Ofer Heifetz 
Cc: stable@vger.kernel.org
Signed-off-by: Vinod Koul

dmaengine: Remove FSF mailing addresses

2015-03-16T16:58:15+00:00

Free Software Foundation mailing address has been moved in the past and some
of the addresses here are outdated. Remove them from file headers since the
COPYING file in the kernel sources includes it.

Signed-off-by: Jarkko Nikula 
Signed-off-by: Vinod Koul

dma: mv_xor: Add support for DMA_INTERRUPT

2014-09-23T14:47:01+00:00

The driver is capable of supporting DMA_INTERRUPT by issuing a dummy 128-byte
transfer. This helps removing a poll in the async_tx stack, replacing it with
a completion interrupt.

Signed-off-by: Lior Amsalem 
Signed-off-by: Ezequiel Garcia 
Signed-off-by: Vinod Koul