linux-toradex.git/drivers/dma, branch PD13.0.0alpha

ENGR00219342: edma: Updated edma driver and edma test driver

2012-09-12T20:50:00+00:00

This patch is to update Edma driver after debugging on board.
mainly, fixed the bug that resulting the request source of DMA1 overflow

Signed-off-by: Xiaochun Li

ENGR00180936-3: add the module for test eDMA driver

2012-09-12T20:49:56+00:00

This patch is to tests eDMA driver.
a simple memory to memory transfer with a 32 bit
source and destination transfer size that generates
an interrupt when the transfer is complete.

Signed-off-by: Xiaochun Li

ENGR00180936-2: edma: add edma driver support for MVF

2012-09-12T20:49:46+00:00

Add EDMA driver support for MVF.

can use the "Always enable" model and DMA request sources
from DMA1.

Signed-off-by: Jingchang Lu 
Signed-off-by: Xiaochun Li

ENGR00174299-1: driver part: Add ePxP v2 DMAENGINE driver

2012-02-14T15:32:27+00:00

add ePxP v2 DMAENGINE driver

Signed-off-by: Robby Cai

ENGR00173731-6 MX6Q/DMA : enable the mxs-dma for mx6q

2012-02-07T08:13:07+00:00

enable the mxs-dma for mx6q.

Signed-off-by: Huang Shijie

ENGR00173731-3 mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()

2012-02-07T08:13:06+00:00

[1] Background :
    The GPMI does ECC read page operation with a DMA chain consist of three DMA
    Command Structures. The middle one of the chain is used to enable the BCH,
    and read out the NAND page.

    The WAIT4END(wait for command end) is a comunication signal between
    the GPMI and MXS-DMA.

[2] The current DMA code sets the WAIT4END bit at the last one, such as:

    +-----+               +-----+                      +-----+
    | cmd | ------------> | cmd | ------------------>  | cmd |
    +-----+               +-----+                      +-----+
                                                          ^
                                                          |
                                                          |
                                                     set WAIT4END here

    This chain works fine in the mx23/mx28.

[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
    be set not only at the last DMA Command Structure,
    but also at the middle one, such as:

    +-----+               +-----+                      +-----+
    | cmd | ------------> | cmd | ------------------>  | cmd |
    +-----+               +-----+                      +-----+
                             ^                            ^
                             |                            |
                             |                            |
                        set WAIT4END here too        set WAIT4END here

    If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
    In the next ECC write page operation, a DMA-timeout occurs.
    This has been catched in the MX6Q board.

[4] In order to fix the bug, rewrite the last parameter of
    mxs_dma_prep_slave_sg(), and use the dma_ctrl_flags:
    ---------------------------------------------------------
      DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
      DMA_CTRL_ACK       : set the WAIT4END bit for this DMA Command Structure.
    ---------------------------------------------------------

[5] changes to the relative drivers:
    For gpmi-nand driver: use the new flags.

Signed-off-by: Huang Shijie

ENGR00173731-2 mxs-dma : use the new mxs-dma.h

2012-02-07T08:13:06+00:00

use the new header : mxs-dma.h.

Signed-off-by: Huang Shijie

dma: mxs-dma: convert to clk_prepare/clk_unprepare

2012-01-31T07:30:47+00:00

The patch converts mxs-dma driver to clk_prepare/clk_unprepare by
using helper functions clk_prepare_enable/clk_disable_unprepare.

Signed-off-by: Shawn Guo 
Acked-by: Marek Vasut 
Acked-by: Vinod Koul

dma: mxs-dma: Don't use CLKGATE bits in CTRL0 to disable DMA channels

2012-01-31T07:20:17+00:00

This is how the original Freescale code (unintentionally) worked,
because the code path which would have asserted the CLKGATE bit was
never actually reached in their code.
This fixes the nefarious "DMA timout" bug when multiple DMA channels
(e.g. GPMI NAND and MMC) are used at the same time.
If a better fix for this problem should be found, the clkgate handling
could be reinstated.
See http://lists.infradead.org/pipermail/linux-arm-kernel/2011-September/065228.html

Also reverse the order of mxs_dma_disable_chan() and
mxs_dma_reset_chan() in mxs_dma_control() because mxs_dma_reset_chan()
can only work when the DMA channel is enabled.

Signed-off-by: Lothar Waßmann 
Signed-off-by: Vinod Koul

dma: mxs-dma: make mxs_dma_prep_slave_sg() multi user safe

2012-01-31T07:19:51+00:00

Using a static variable for counting the number of CCWs attached to
a DMA channel when appending a new descriptor is not multi user safe.

Signed-off-by: Lothar Waßmann 
Signed-off-by: Vinod Koul