linux-toradex.git/drivers/edac/Kconfig, branch v5.5 Linux kernel for Apalis and Colibri modules riscv: move sifive_l2_cache.c to drivers/soc 2019-12-20T11:40:24+00:00 Christoph Hellwig hch@lst.de 2019-11-07T09:20:39+00:00 9209fb51896fe0eef8dfac85afe1f357e9265c0d The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Borislav Petkov <bp@suse.de> [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> 
The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management.  It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.

Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
[paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
 Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm 2019-09-22T16:39:09+00:00 Linus Torvalds torvalds@linux-foundation.org 2019-09-22T16:39:09+00:00 8808cf8cbc4da1ceef9307fba7e499563908c211 Pull ARM updates from Russell King: - fix various clang build and cppcheck issues - switch ARM to use new common outgoing-CPU-notification code - add some additional explanation about the boot code - kbuild "make clean" fixes - get rid of another "(____ptrval____)", this time for the VDSO code - avoid treating cache maintenance faults as a write - add a frame pointer unwinder implementation for clang - add EDAC support for Aurora L2 cache - improve robustness of adjust_lowmem_bounds() finding the bounds of lowmem. - add reset control for AMBA primecell devices * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (24 commits) ARM: 8906/1: drivers/amba: add reset control to amba bus probe ARM: 8905/1: Emit __gnu_mcount_nc when using Clang 10.0.0 or newer ARM: 8904/1: skip nomap memblocks while finding the lowmem/highmem boundary ARM: 8903/1: ensure that usable memory in bank 0 starts from a PMD-aligned address ARM: 8891/1: EDAC: armada_xp: Add support for more SoCs ARM: 8888/1: EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC ARM: 8892/1: EDAC: Add missing debugfs_create_x32 wrapper ARM: 8890/1: l2x0: add marvell,ecc-enable property for aurora ARM: 8889/1: dt-bindings: document marvell,ecc-enable binding ARM: 8886/1: l2x0: support parity-enable/disable on aurora ARM: 8885/1: aurora-l2: add defines for parity and ECC registers ARM: 8887/1: aurora-l2: add prefix to MAX_RANGE_SIZE ARM: 8902/1: l2c: move cache-aurora-l2.h to asm/hardware ARM: 8900/1: UNWINDER_FRAME_POINTER implementation for Clang ARM: 8898/1: mm: Don't treat faults reported from cache maintenance as writes ARM: 8896/1: VDSO: Don't leak kernel addresses ARM: 8895/1: visit mach-* and plat-* directories when cleaning ARM: 8894/1: boot: Replace open-coded nop with macro ARM: 8893/1: boot: Explain the 8 nops ARM: 8876/1: fix O= building with CONFIG_FPE_FASTFPE ... 
Pull ARM updates from Russell King:

 - fix various clang build and cppcheck issues

 - switch ARM to use new common outgoing-CPU-notification code

 - add some additional explanation about the boot code

 - kbuild "make clean" fixes

 - get rid of another "(____ptrval____)", this time for the VDSO code

 - avoid treating cache maintenance faults as a write

 - add a frame pointer unwinder implementation for clang

 - add EDAC support for Aurora L2 cache

 - improve robustness of adjust_lowmem_bounds() finding the bounds of
   lowmem.

 - add reset control for AMBA primecell devices

* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (24 commits)
  ARM: 8906/1: drivers/amba: add reset control to amba bus probe
  ARM: 8905/1: Emit __gnu_mcount_nc when using Clang 10.0.0 or newer
  ARM: 8904/1: skip nomap memblocks while finding the lowmem/highmem boundary
  ARM: 8903/1: ensure that usable memory in bank 0 starts from a PMD-aligned address
  ARM: 8891/1: EDAC: armada_xp: Add support for more SoCs
  ARM: 8888/1: EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC
  ARM: 8892/1: EDAC: Add missing debugfs_create_x32 wrapper
  ARM: 8890/1: l2x0: add marvell,ecc-enable property for aurora
  ARM: 8889/1: dt-bindings: document marvell,ecc-enable binding
  ARM: 8886/1: l2x0: support parity-enable/disable on aurora
  ARM: 8885/1: aurora-l2: add defines for parity and ECC registers
  ARM: 8887/1: aurora-l2: add prefix to MAX_RANGE_SIZE
  ARM: 8902/1: l2c: move cache-aurora-l2.h to asm/hardware
  ARM: 8900/1: UNWINDER_FRAME_POINTER implementation for Clang
  ARM: 8898/1: mm: Don't treat faults reported from cache maintenance as writes
  ARM: 8896/1: VDSO: Don't leak kernel addresses
  ARM: 8895/1: visit mach-* and plat-* directories when cleaning
  ARM: 8894/1: boot: Replace open-coded nop with macro
  ARM: 8893/1: boot: Explain the 8 nops
  ARM: 8876/1: fix O= building with CONFIG_FPE_FASTFPE
  ...
ARM: 8888/1: EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC 2019-08-29T06:58:01+00:00 Jan Luebbe jlu@pengutronix.de 2019-07-12T04:46:57+00:00 7f6998a41257a8930ee5b6866ba56a25230841ed Add support for the ECC functionality as found in the DDR RAM and L2 cache controllers on the MV78230/MV78x60 SoCs. This driver has been tested on the MV78460 (on a custom board with a DDR3 ECC DIMM). [cp use SPDX license] Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Borislav Petkov <bp@suse.de> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> 
Add support for the ECC functionality as found in the DDR RAM and L2
cache controllers on the MV78230/MV78x60 SoCs. This driver has been
tested on the MV78460 (on a custom board with a DDR3 ECC DIMM).

[cp use SPDX license]

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
EDAC, mellanox: Add ECC support for BlueField DDR4 2019-08-08T15:57:01+00:00 Shravan Kumar Ramani sramani@mellanox.com 2019-06-25T19:13:59+00:00 82413e562ea6eadfb6de946dcc6f74af31d64e7f Add ECC support for Mellanox BlueField SoC DDR controller. This requires SMC to the running Arm Trusted Firmware to report what is the current memory configuration. Reviewed-by: James Morse <james.morse@arm.com> Signed-off-by: Shravan Kumar Ramani <sramani@mellanox.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> 
Add ECC support for Mellanox BlueField SoC DDR controller.
This requires SMC to the running Arm Trusted Firmware to report
what is the current memory configuration.

Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Shravan Kumar Ramani <sramani@mellanox.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
EDAC/sifive: Add EDAC platform driver for SiFive SoCs 2019-06-20T18:44:36+00:00 Yash Shah yash.shah@sifive.com 2019-05-06T11:27:06+00:00 91abaeaaff35d97e88d2249f69f19db749a19a68 Add an EDAC driver for SiFive SoCs. The initial version supports ECC event monitoring and reporting through the EDAC framework for the SiFive L2 cache controller. It registers for notifier events from the L2 cache controller driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events. [ bp: Massage commit message. ] Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: James Morse <james.morse@arm.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: linux-riscv@lists.infradead.org Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: "Paul E. McKenney" <paulmck@linux.ibm.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: sachin.ghadi@sifive.com Link: https://lkml.kernel.org/r/1557142026-15949-2-git-send-email-yash.shah@sifive.com 
Add an EDAC driver for SiFive SoCs. The initial version supports ECC
event monitoring and reporting through the EDAC framework for the SiFive
L2 cache controller. It registers for notifier events from the L2 cache
controller driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events.

 [ bp: Massage commit message. ]

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: James Morse <james.morse@arm.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: linux-riscv@lists.infradead.org
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: "Paul E. McKenney" <paulmck@linux.ibm.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: sachin.ghadi@sifive.com
Link: https://lkml.kernel.org/r/1557142026-15949-2-git-send-email-yash.shah@sifive.com
EDAC/mpc85xx: Prevent building as a module 2019-05-10T18:15:11+00:00 Michael Ellerman mpe@ellerman.id.au 2019-05-02T14:19:41+00:00 2b8358a951b1e2a534a54924cd8245e58a1c5fb8 The mpc85xx EDAC driver can be configured as a module but then fails to build because it uses two unexported symbols: ERROR: ".pci_find_hose_for_OF_device" [drivers/edac/mpc85xx_edac_mod.ko] undefined! ERROR: ".early_find_capability" [drivers/edac/mpc85xx_edac_mod.ko] undefined! We don't want to export those symbols just for this driver, so make the driver only configurable as a built-in. This seems to have been broken since at least c92132f59806 ("edac/85xx: Add PCIe error interrupt edac support") (Nov 2013). [ bp: make it depend on EDAC=y so that the EDAC core doesn't get built as a module. ] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Johannes Thumshirn <jth@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: linuxppc-dev@ozlabs.org Cc: morbidrsa@gmail.com Link: https://lkml.kernel.org/r/20190502141941.12927-1-mpe@ellerman.id.au 
The mpc85xx EDAC driver can be configured as a module but then fails to
build because it uses two unexported symbols:

  ERROR: ".pci_find_hose_for_OF_device" [drivers/edac/mpc85xx_edac_mod.ko] undefined!
  ERROR: ".early_find_capability" [drivers/edac/mpc85xx_edac_mod.ko] undefined!

We don't want to export those symbols just for this driver, so make the
driver only configurable as a built-in.

This seems to have been broken since at least

  c92132f59806 ("edac/85xx: Add PCIe error interrupt edac support")

(Nov 2013).

 [ bp: make it depend on EDAC=y so that the EDAC core doesn't get built
   as a module. ]

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Johannes Thumshirn <jth@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: linuxppc-dev@ozlabs.org
Cc: morbidrsa@gmail.com
Link: https://lkml.kernel.org/r/20190502141941.12927-1-mpe@ellerman.id.au
EDAC/altera: Add separate SDRAM EDAC config 2019-02-26T15:18:57+00:00 Thor Thayer thor.thayer@linux.intel.com 2019-02-25T18:56:45+00:00 580b5cf50ca8f4781961382d54959683341b3126 The CONFIG_ALTERA_EDAC Kconfig symbol always enables the SDRAM EDAC functionality. On the newer architectures, however, there are cases where the peripheral EDAC functionality is enabled but SDRAM needs to be disabled. Move SDRAM functions so they can be contained inside the conditional CONFIG. Create new CONFIG option just for SDRAM. [ bp: Massage commit message. ] Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: James Morse <james.morse@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: dinguyen@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: linux@armlinux.org.uk Link: https://lkml.kernel.org/r/1551121006-4657-2-git-send-email-thor.thayer@linux.intel.com 
The CONFIG_ALTERA_EDAC Kconfig symbol always enables the SDRAM EDAC
functionality. On the newer architectures, however, there are cases
where the peripheral EDAC functionality is enabled but SDRAM needs to be
disabled.

Move SDRAM functions so they can be contained inside the conditional
CONFIG. Create new CONFIG option just for SDRAM.

 [ bp: Massage commit message. ]

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: James Morse <james.morse@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: dinguyen@kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: linux@armlinux.org.uk
Link: https://lkml.kernel.org/r/1551121006-4657-2-git-send-email-thor.thayer@linux.intel.com
EDAC, i10nm: Fix randconfig builds 2019-02-06T09:40:58+00:00 Tony Luck tony.luck@intel.com 2019-02-05T18:02:00+00:00 d6a9f7336d925364daca00557afa59a68e78b422 I10NM_EDAC depends on CONFIG_ACPI so make that dependency explicit. Reported-by: Borislav Petkov <bp@suse.de> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Aristeu Rozanski <aris@redhat.com> Cc: James Morse <james.morse@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: https://lkml.kernel.org/r/20190205180200.26865-1-tony.luck@intel.com 
I10NM_EDAC depends on CONFIG_ACPI so make that dependency explicit.

Reported-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Aristeu Rozanski <aris@redhat.com>
Cc: James Morse <james.morse@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: https://lkml.kernel.org/r/20190205180200.26865-1-tony.luck@intel.com
EDAC, i10nm: Add a driver for Intel 10nm server processors 2019-02-02T12:33:18+00:00 Qiuxu Zhuo qiuxu.zhuo@intel.com 2019-01-30T19:15:19+00:00 d4dc89d069aab9074e2493a4c2f3969a0a0b91c1 This driver supports the Intel 10nm series server integrated memory controller. It gets the memory capacity and topology information by reading the registers in PCI configuration space and memory-mapped I/O. It decodes the memory error address to the platform specific address by using the ACPI Address Translation (ADXL) Device Specific Method (DSM). Co-developed-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: James Morse <james.morse@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: linux-edac <linux-edac@vger.kernel.org> Link: https://lkml.kernel.org/r/20190130191519.15393-5-tony.luck@intel.com 
This driver supports the Intel 10nm series server integrated memory
controller. It gets the memory capacity and topology information by
reading the registers in PCI configuration space and memory-mapped I/O.

It decodes the memory error address to the platform specific address
by using the ACPI Address Translation (ADXL) Device Specific Method
(DSM).

Co-developed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: James Morse <james.morse@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: https://lkml.kernel.org/r/20190130191519.15393-5-tony.luck@intel.com
EDAC, aspeed: Add an Aspeed AST2500 EDAC driver 2019-01-18T14:23:11+00:00 Stefan M Schaeckeler sschaeck@cisco.com 2019-01-17T16:38:16+00:00 9b7e6242ee4efcd7f9ef699bf1965e3a5343f216 Add support for the Aspeed AST2500 SoC. Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: https://lkml.kernel.org/r/1547743097-5236-2-git-send-email-schaecsn@gmx.net 
Add support for the Aspeed AST2500 SoC.

Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-aspeed@lists.ozlabs.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: https://lkml.kernel.org/r/1547743097-5236-2-git-send-email-schaecsn@gmx.net