linux-toradex.git/drivers/edac/Makefile, branch v4.1-rc4

EDAC, synps: Add EDAC support for zynq ddr ecc controller

2015-01-07T10:42:05+00:00

Add EDAC support for ecc errors reporting on the synopsys ddr
controller. The ddr ecc controller corrects single bit errors and
detects double bit errors.

Selected important-ish notes from the changelog:

- I have not taken care of spliting synps_edac_geterror_info function as
it adds additional indentation levels and moreover the existing changes
were made as part of the v2 review comments

- Removed dt binding info as already there is a binding info available
under memorycontroller. so, updated ecc info there.

- Shortened the prefix "sysnopsys" to "synps"

Signed-off-by: Punnaiah Choudary Kalluri 
Link: http://lkml.kernel.org/r/a728a8d4678f4dbf9de189a480297c3d@BY2FFO11FD034.protection.gbl
[ Boris: massage commit message. ]
Signed-off-by: Borislav Petkov

EDAC, pci_sysfs: remove unneccessary ifdef around entire file

2014-11-11T17:17:57+00:00

The file edac_pci_sysfs.c is dependent on CONFIG_PCI. This is already
modelled in the Makefile, but edac_pci_sysfs.o is still contained in
the list of files compiled even without CONFIG_PCI.

This change removes edac_pci_sysfs.o from the list of built objects
when not having CONFIG_PCI enabled and removes the then-unnecessary
ifdef from the source file.

Signed-off-by: Andreas Ruprecht 
Link: http://lkml.kernel.org/r/1407697803-3837-1-git-send-email-rupran@einserver.de
Signed-off-by: Borislav Petkov

edac: altera: Add Altera SDRAM EDAC support

2014-09-04T18:41:46+00:00

This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.

There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]

[1] https://lkml.org/lkml/2014/7/30/514

[dinguyen] Fixed Kconfig to have EDAC_ALTERA_MC as a tristate to prevent a
build failure for allmodconfig.

Signed-off-by: Thor Thayer 
Acked-by: Borislav Petkov 
[dinguyen] cleaned up commit message
Signed-off-by: Dinh Nguyen

ie31200_edac: Introduce the driver

2014-07-04T12:00:26+00:00

Add a driver for the E3-1200 series of Intel DRAM controllers, based on
the following E3-1200 specs:

http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200v3-vol-2-datasheet.html

I've tested this on bad memory hardware, and observed correlating bad
reads and uncorrected memory errors as reported by the driver.

Tested against:

CPU E3-1270 v3 @ 3.50GHz : 8086:0c08 (haswell)
CPU E3-1270 V2 @ 3.50GHz : 8086:0158 (ivy bridge)
CPU E31270 @ 3.40GHz : 8086:0108 (sandy bridge)

Signed-off-by: Jason Baron 
Link: http://lkml.kernel.org/r/95c83e80dd40b5377e8bb206285c5d95ac623872.1403818526.git.jbaron@akamai.com
[ Boris: realign defines ]
Signed-off-by: Borislav Petkov

ghes_edac: Register at EDAC core the BIOS report

2013-02-25T22:42:12+00:00

Register GHES at EDAC MC core, in order to avoid other
drivers to also handle errors and mangle with error data.

The edac core will warrant that just one driver will be used,
so the first one to register (BIOS first) will be the one that
will be reporting the hardware errors.

For now, the EDAC driver does nothing but to register at the
EDAC core, preventing the hardware-driven mechanism to
interfere with GHES.

Signed-off-by: Mauro Carvalho Chehab

MIPS: Cavium: Add EDAC support.

2012-12-12T15:48:49+00:00

Drivers for EDAC on Cavium.  Supported subsystems are:

 o CPU primary caches.  These are parity protected only, so only error
   reporting.
 o Second level cache - ECC protected, provides SECDED.
 o Memory: ECC / SECDEC if used with suitable DRAM modules.  The driver will
   will only initialize if ECC is enabled on a system so is safe to run on
   non-ECC memory.
 o PCI: Parity error reporting

Since it is very hard to test this sort of code the implementation is very
conservative and uses polling where possible for now.

Signed-off-by: Ralf Baechle 
Reviewed-by: Borislav Petkov

edac: add support for Calxeda highbank L2 cache ecc

2012-06-27T12:01:29+00:00

Add support for L2 ECC on Calxeda highbank platform.

Signed-off-by: Rob Herring 
Signed-off-by: Mauro Carvalho Chehab

edac: add support for Calxeda highbank memory controller

2012-06-27T12:00:57+00:00

Add support for memory controller on Calxeda Highbank platforms. Highbank
platforms support a single 4GB mini-DIMM with 1-bit correction and 2-bit
detection.

Signed-off-by: Rob Herring 
Signed-off-by: Mauro Carvalho Chehab

edac: sb_edac: Add it to the building system

2011-11-01T12:01:54+00:00

Some changes on it were required due to changeset cd90cc84c6bf0, that
changed the glue with the MCE logic.

Signed-off-by: Mauro Carvalho Chehab

i7core_edac: Drop the edac_mce facility

2011-11-01T12:01:24+00:00

Remove edac_mce pieces and use the normal MCE decoder notifier chain by
retaining the same functionality with considerably less code.

Signed-off-by: Borislav Petkov 
Signed-off-by: Mauro Carvalho Chehab