linux-toradex.git/drivers/edac/amd64_edac.h, branch v3.9.4

amd64_edac: Fix type usage in NB IDs and memory ranges

2013-01-10T15:18:00+00:00

Use appropriate types for northbridge IDs and memory ranges. Mark
immutable data const and keep within compilation unit on related
structures.

Signed-off-by: Daniel J Blueman 
Link: http://lkml.kernel.org/r/1354265060-22956-2-git-send-email-daniel@numascale-asia.com
[Boris: Drop arg change to node_to_amd_nb]
Signed-off-by: Borislav Petkov

x86, AMD, NB: Add multi-domain support

2013-01-10T15:17:58+00:00

Fix get_node_id to match northbridge IDs from the array of detected
ones, allowing multi-server support such as with Numascale's
NumaConnect, renaming to 'amd_get_node_id' for consistency.

Signed-off-by: Daniel J Blueman 
Link: http://lkml.kernel.org/r/1353997932-8475-1-git-send-email-daniel@numascale-asia.com
[Boris: shorten lines to fit 80 cols]
Signed-off-by: Borislav Petkov

amd64_edac: Use DBAM_DIMM macro

2012-11-28T10:46:19+00:00

Instead of open-coding it, use the DBAM_DIMM macro in
amd64_csrow_nr_pages() which we have already.

Signed-off-by: Borislav Petkov

amd64_edac: Reorganize error reporting path

2012-11-28T10:45:34+00:00

Rewrite CE/UE paths so that they use the same code and drop additional
code duplication in handle_ue. Add a struct err_info which collects
required info for the error reporting. This, in turn, helps slimming all
edac_mc_handle_error() calls down to one.

Signed-off-by: Borislav Petkov

amd64_edac: Improve error injection

2012-11-28T10:45:01+00:00

When injecting DRAM ECC errors over the F3xB[8,C] interface, the machine
does this by injecting the error in the next non-cached access. This
takes relatively long time on a normal system so that in order for us to
expedite it, we disable the caches around the injection.

Signed-off-by: Borislav Petkov

amd64_edac: Cleanup error injection code

2012-11-28T10:44:35+00:00

Invert kstrtoul return value testing and win one indentation level.
Also, shorten up macro names so that the lines can fit into 80 cols. No
functional change.

Signed-off-by: Borislav Petkov

EDAC: Change Boris' email address

2012-10-30T09:05:51+00:00

My @amd.com address will be invalid soon so move to private
email address.

Signed-off-by: Borislav Petkov 
Link: http://lkml.kernel.org/r/1351532410-4887-2-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar

amd64_edac: convert sysfs logic to use struct device

2012-06-11T16:23:40+00:00

Now that the EDAC core supports struct device, there's no sense
on having any logic at the EDAC core to simulate it. So, instead
of adding such logic there, change the logic at amd64_edac to
use it.

Reviewed-by: Aristeu Rozanski 
Cc: Doug Thompson 
Cc: Borislav Petkov 
Signed-off-by: Mauro Carvalho Chehab

amd64_edac: Erratum #637 workaround

2011-04-26T14:18:56+00:00

F15h CPUs may report a non-DRAM address when reporting an error address
belonging to a CC6 state save area. Add a workaround to detect this
condition and compute the actual DRAM address of the error as documented
in the Revision Guide for AMD Family 15h Models 00h-0Fh Processors.

Signed-off-by: Borislav Petkov

amd64_edac: Factor in CC6 save area

2011-04-26T14:18:44+00:00

F15h and later use a portion of DRAM as a CC6 storage area. BIOS
programs D18F1x[17C:140,7C:40] DRAM Base/Limit accordingly by
subtracting the storage area from the DRAM limit setting. However, in
order for edac to consider that part of DRAM too, we need to include it
into the per-node range.

Signed-off-by: Borislav Petkov