linux-toradex.git/drivers/fpga/Makefile, branch v4.12

fpga: Add support for Xilinx LogiCORE PR Decoupler

2017-04-08T15:50:36+00:00

This adds support for the Xilinx LogiCORE PR Decoupler
soft-ip that does decoupling of PR regions in the FPGA
fabric during partial reconfiguration.

Signed-off-by: Moritz Fischer 
Signed-off-by: Michal Simek 
Cc: Sören Brinkmann 
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

2017-04-08T15:45:28+00:00

This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.

Signed-off-by: Matthew Gerlach 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

2017-04-08T15:45:28+00:00

Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga manager: Add Xilinx slave serial SPI driver

2017-04-08T15:45:28+00:00

The driver loads FPGA firmware over SPI, using the "slave serial"
configuration interface on Xilinx FPGAs.

Signed-off-by: Anatolij Gustschin 
Acked-by: Michal Simek 
Reviewed-by: Moritz Fischer 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: Add support for Lattice iCE40 FPGAs

2017-03-17T06:10:48+00:00

This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.

Signed-off-by: Joel Holdsworth 
Reviewed-by: Marek Vasut 
Reviewed-by: Moritz Fischer 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

FPGA: Add TS-7300 FPGA manager

2017-03-17T06:10:48+00:00

Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.

The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.

Signed-off-by: Florian Fainelli 
Acked-by: Alan Tull 
Acked-by: Moritz Fischer 
Signed-off-by: Greg Kroah-Hartman

fpga-manager: Add Socfpga Arria10 support

2016-11-10T16:03:36+00:00

Add low level driver to support reprogramming FPGAs for Altera
SoCFPGA Arria10.

Signed-off-by: Alan Tull 
Reviewed-by: Moritz Fischer 
Signed-off-by: Greg Kroah-Hartman

fpga: add altera freeze bridge support

2016-11-10T16:03:36+00:00

Add a low level driver for Altera Freeze Bridges to the FPGA Bridge
framework.  A freeze bridge is a bridge that exists in the FPGA
fabric to isolate one region of the FPGA from the busses while that
one region is being reprogrammed.

Signed-off-by: Alan Tull 
Signed-off-by: Matthew Gerlach 
Signed-off-by: Greg Kroah-Hartman

ARM: socfpga: fpga bridge driver support

2016-11-10T16:03:36+00:00

Supports Altera SOCFPGA bridges:
 * fpga2sdram
 * fpga2hps
 * hps2fpga
 * lwhps2fpga

Allows enabling/disabling the bridges through the FPGA
Bridge Framework API functions.

The fpga2sdram driver only supports enabling and disabling
of the ports that been configured early on.  This is due to
a hardware limitation where the read, write, and command
ports on the fpga2sdram bridge can only be reconfigured
while there are no transactions to the sdram, i.e. when
running out of OCRAM before the kernel boots.

Device tree property 'init-val' configures the driver to
enable or disable the bridge during probe.  If the property
does not exist, the driver will leave the bridge in its
current state.

Signed-off-by: Alan Tull 
Signed-off-by: Matthew Gerlach 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Greg Kroah-Hartman

fpga: fpga-region: device tree control for FPGA

2016-11-10T16:03:35+00:00

FPGA Regions support programming FPGA under control of the Device
Tree.

Signed-off-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman