linux-toradex.git/drivers/fpga/Makefile, branch v5.0

fpga: add intel stratix10 soc fpga manager driver

2018-11-26T19:15:07+00:00

Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel service layer driver
which does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.

Signed-off-by: Alan Tull 
Signed-off-by: Richard Gong 
Acked-by: Moritz Fischer 
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support

2018-07-15T11:55:47+00:00

DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user memory regions
for dma, and unmap them after use. Iova is returned from driver to user
space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to
unmap it after use, otherwise, driver will unmap them in device file
release operation.

Each AFU has its own rb tree to keep track of its mapped DMA regions.

Ioctl interfaces:
* DFL_FPGA_PORT_DMA_MAP
  Do the dma mapping per user_addr and length provided by user.
  Return iova in provided struct dfl_fpga_port_dma_map.

* DFL_FPGA_PORT_DMA_UNMAP
  Unmap the dma region per iova provided by user.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Xiao Guangrong 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: afu: add afu sub feature support

2018-07-15T11:55:47+00:00

User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid PR bitstream is programmed and the port is enabled,
then this MMIO region could be accessed.

This patch adds support to enumerate the AFU MMIO region and expose it
to userspace via mmap file operation. Below interfaces are exposed to user:

Sysfs interface:
* /sys/class/fpga_region///afu_id
  Read-only. Indicate which PR bitstream is programmed to this AFU.

Ioctl interfaces:
* DFL_FPGA_PORT_GET_INFO
  Provide info to userspace on the number of supported region.
  Only UAFU region is supported now.

* DFL_FPGA_PORT_GET_REGION_INFO
  Provide region information, including access permission, region size,
  offset from the start of device fd.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Xiao Guangrong 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: add FPGA Accelerated Function Unit driver basic framework

2018-07-15T11:55:46+00:00

On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
reprogrammed for different functions. It connects to the FPGA
infrastructure (static FPGA region) via a Port. Port CSRs are
implemented separately from the AFU CSRs to provide control and
status of the Port. Once valid PR bitstream is programmed into
the AFU, it allows access to the AFU CSRs in the AFU MMIO space.

This patch only implements basic driver framework for AFU, including
device file operation framework.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Xiao Guangrong 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: add fpga region platform driver for FME

2018-07-15T11:55:46+00:00

This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Acked-by: Moritz Fischer 
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: add fpga bridge platform driver for FME

2018-07-15T11:55:46+00:00

This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set callback for fpga bridge.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Acked-by: Moritz Fischer 
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: add fpga manager platform driver for FME

2018-07-15T11:55:46+00:00

This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Kang Luwei 
Signed-off-by: Xiao Guangrong 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: fme: add partial reconfiguration sub feature support

2018-07-15T11:55:46+00:00

Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).

It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
and invokes fpga-region's interface (fpga_region_program_fpga) for PR
operation once PR request received via ioctl. Below user space interface
is exposed by this sub feature.

Ioctl interface:
* DFL_FPGA_FME_PORT_PR
  Do partial reconfiguration per information from userspace, including
  target port(AFU), buffer size and address info. It returns error code
  to userspace if failed. For detailed PR error information, user needs
  to read fpga-mgr's status sysfs interface.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Kang Luwei 
Signed-off-by: Xiao Guangrong 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga: dfl: add FPGA Management Engine driver basic framework

2018-07-15T11:55:45+00:00

The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'. It's a platform device created by
DFL framework.

This patch adds the basic framework of FME platform driver. It defines
sub feature drivers to handle the different sub features, including init,
uinit and ioctl. It also registers the file operations for the device file.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Kang Luwei 
Signed-off-by: Xiao Guangrong 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Acked-by: Moritz Fischer 
Signed-off-by: Greg Kroah-Hartman

fpga: add FPGA DFL PCIe device driver

2018-07-15T11:55:45+00:00

This patch implements the basic framework of the driver for FPGA PCIe
device which implements the Device Feature List (DFL) in its MMIO space.
This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including
both integrated (e.g. Intel Server Platform with In-package FPGA) and
discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions.

Signed-off-by: Tim Whisonant 
Signed-off-by: Enno Luebbers 
Signed-off-by: Shiva Rao 
Signed-off-by: Christopher Rauer 
Signed-off-by: Zhang Yi 
Signed-off-by: Xiao Guangrong 
Signed-off-by: Wu Hao 
Acked-by: Alan Tull 
Acked-by: Moritz Fischer 
Signed-off-by: Greg Kroah-Hartman