<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/fpga/altera-cvp.c, branch v7.0-rc2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>fpga: altera-cvp: Use pci_find_vsec_capability() when probing FPGA device</title>
<updated>2025-11-10T07:03:13+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2025-11-09T20:16:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c9243d6df0d617535e842aa4c3d1d7dfdb91d07b'/>
<id>c9243d6df0d617535e842aa4c3d1d7dfdb91d07b</id>
<content type='text'>
Currently altera_cvp_probe() open-codes pci_find_vsec_capability().
Refactor the former to use the latter.

With that done:
- use the VSEC ID as per datasheet [1]
- update the error message accordingly

Link: https://www.intel.com/content/www/us/en/docs/programmable/683763/23-1/vendor-specific-header-register.html [1]
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20251109201729.3220460-1-andriy.shevchenko@linux.intel.com
Reviewed-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Xu Yilun &lt;yilun.xu@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently altera_cvp_probe() open-codes pci_find_vsec_capability().
Refactor the former to use the latter.

With that done:
- use the VSEC ID as per datasheet [1]
- update the error message accordingly

Link: https://www.intel.com/content/www/us/en/docs/programmable/683763/23-1/vendor-specific-header-register.html [1]
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20251109201729.3220460-1-andriy.shevchenko@linux.intel.com
Reviewed-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Xu Yilun &lt;yilun.xu@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: altera-cvp: Increase credit timeout</title>
<updated>2025-03-01T09:36:58+00:00</updated>
<author>
<name>Kuhanh Murugasen Krishnan</name>
<email>kuhanh.murugasen.krishnan@intel.com</email>
</author>
<published>2025-02-12T22:12:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0f05886a40fdc55016ba4d9ae0a9c41f8312f15b'/>
<id>0f05886a40fdc55016ba4d9ae0a9c41f8312f15b</id>
<content type='text'>
Increase the timeout for SDM (Secure device manager) data credits from
20ms to 40ms. Internal stress tests running at 500 loops failed with the
current timeout of 20ms. At the start of a FPGA configuration, the CVP
host driver reads the transmit credits from SDM. It then sends bitstream
FPGA data to SDM based on the total credits. Each credit allows the
CVP host driver to send 4kBytes of data. There are situations whereby,
the SDM did not respond in time during testing.

Signed-off-by: Ang Tien Sung &lt;tien.sung.ang@intel.com&gt;
Signed-off-by: Kuhanh Murugasen Krishnan &lt;kuhanh.murugasen.krishnan@intel.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20250212221249.2715929-1-tien.sung.ang@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Increase the timeout for SDM (Secure device manager) data credits from
20ms to 40ms. Internal stress tests running at 500 loops failed with the
current timeout of 20ms. At the start of a FPGA configuration, the CVP
host driver reads the transmit credits from SDM. It then sends bitstream
FPGA data to SDM based on the total credits. Each credit allows the
CVP host driver to send 4kBytes of data. There are situations whereby,
the SDM did not respond in time during testing.

Signed-off-by: Ang Tien Sung &lt;tien.sung.ang@intel.com&gt;
Signed-off-by: Kuhanh Murugasen Krishnan &lt;kuhanh.murugasen.krishnan@intel.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20250212221249.2715929-1-tien.sung.ang@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: altera-cvp: Remove an unused field in struct altera_cvp_conf</title>
<updated>2024-04-02T06:31:08+00:00</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2024-04-01T13:08:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f6c86fdf3716c9257612f8f001c6e95db84fb844'/>
<id>f6c86fdf3716c9257612f8f001c6e95db84fb844</id>
<content type='text'>
In "struct altera_cvp_conf", the 'mgr' field is unused.
Remove it.

Found with cppcheck, unusedStructMember.

Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/7986690e79fa6f7880bc1db783cb0e46a1c2723e.1711976883.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Xu Yilun &lt;yilun.xu@linux.intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In "struct altera_cvp_conf", the 'mgr' field is unused.
Remove it.

Found with cppcheck, unusedStructMember.

Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/7986690e79fa6f7880bc1db783cb0e46a1c2723e.1711976883.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Xu Yilun &lt;yilun.xu@linux.intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: mgr: Use standard dev_release for class driver</title>
<updated>2021-11-28T21:59:13+00:00</updated>
<author>
<name>Russ Weight</name>
<email>russell.h.weight@intel.com</email>
</author>
<published>2021-11-19T01:55:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4ba0b2c294fe691921271372f7b59e5cc2ce4b0f'/>
<id>4ba0b2c294fe691921271372f7b59e5cc2ce4b0f</id>
<content type='text'>
The FPGA manager class driver data structure is being treated as a
managed resource instead of using the standard dev_release call-back
function to release the class data structure. This change removes
the managed resource code for the freeing of the class data structure
and combines the create() and register() functions into a single
register() or register_full() function.

The register_full() function accepts an info data structure to provide
flexibility in passing optional parameters. The register() function
supports the current parameter list for users that don't require the
use of optional parameters.

The devm_fpga_mgr_register() function is retained, and the
devm_fpga_mgr_register_full() function is added.

Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Reviewed-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The FPGA manager class driver data structure is being treated as a
managed resource instead of using the standard dev_release call-back
function to release the class data structure. This change removes
the managed resource code for the freeing of the class data structure
and combines the create() and register() functions into a single
register() or register_full() function.

The register_full() function accepts an info data structure to provide
flexibility in passing optional parameters. The register() function
supports the current parameter list for users that don't require the
use of optional parameters.

The devm_fpga_mgr_register() function is retained, and the
devm_fpga_mgr_register_full() function is added.

Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Reviewed-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: fix spelling mistakes</title>
<updated>2021-07-22T02:54:21+00:00</updated>
<author>
<name>Tom Rix</name>
<email>trix@redhat.com</email>
</author>
<published>2021-05-19T16:30:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=580e3137318edb39d2c6efa5dad51e3fbd7e2536'/>
<id>580e3137318edb39d2c6efa5dad51e3fbd7e2536</id>
<content type='text'>
Run the fpga subsystem through aspell.

Signed-off-by: Tom Rix &lt;trix@redhat.com&gt;
Reviewed-by: Fernando Pacheco &lt;fpacheco@redhat.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Run the fpga subsystem through aspell.

Signed-off-by: Tom Rix &lt;trix@redhat.com&gt;
Reviewed-by: Fernando Pacheco &lt;fpacheco@redhat.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: altera-cvp: Add Stratix10 (V2) Support</title>
<updated>2019-08-24T18:38:29+00:00</updated>
<author>
<name>Thor Thayer</name>
<email>thor.thayer@linux.intel.com</email>
</author>
<published>2019-08-19T20:48:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=e58915179f3f4a839ea3b9aeae1c1e13e98e33b1'/>
<id>e58915179f3f4a839ea3b9aeae1c1e13e98e33b1</id>
<content type='text'>
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.

Signed-off-by: Thor Thayer &lt;thor.thayer@linux.intel.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.

Signed-off-by: Thor Thayer &lt;thor.thayer@linux.intel.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: altera-cvp: Preparation for V2 parts.</title>
<updated>2019-08-24T18:38:27+00:00</updated>
<author>
<name>Thor Thayer</name>
<email>thor.thayer@linux.intel.com</email>
</author>
<published>2019-08-19T20:48:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d2083d040a95b923a217377dd51c27d57eecf5e6'/>
<id>d2083d040a95b923a217377dd51c27d57eecf5e6</id>
<content type='text'>
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.

Signed-off-by: Thor Thayer &lt;thor.thayer@linux.intel.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.

Signed-off-by: Thor Thayer &lt;thor.thayer@linux.intel.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: altera-cvp: Discover Vendor Specific offset</title>
<updated>2019-08-24T18:38:24+00:00</updated>
<author>
<name>Thor Thayer</name>
<email>thor.thayer@linux.intel.com</email>
</author>
<published>2019-08-19T20:48:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=eb12511f0d47b4da58cc9fc1e93362081fa3331b'/>
<id>eb12511f0d47b4da58cc9fc1e93362081fa3331b</id>
<content type='text'>
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read and write abstraction functions to
handle the offset (altera_read_config_dword() and
altera_write_config_dword()).

Signed-off-by: Thor Thayer &lt;thor.thayer@linux.intel.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read and write abstraction functions to
handle the offset (altera_read_config_dword() and
altera_write_config_dword()).

Signed-off-by: Thor Thayer &lt;thor.thayer@linux.intel.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: altera-cvp: Fix function definition argument</title>
<updated>2019-07-24T21:10:42+00:00</updated>
<author>
<name>Carlos A Petry</name>
<email>capetry.dev@gmail.com</email>
</author>
<published>2018-11-08T01:13:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=998c1de56dac7ff6bad4f810259cc25c7d6d2843'/>
<id>998c1de56dac7ff6bad4f810259cc25c7d6d2843</id>
<content type='text'>
Fix the following checkpatch warning:
WARNING: function definition argument 'struct altera_cvp_conf *'

Signed-off-by: Carlos A Petry &lt;capetry.dev@gmail.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix the following checkpatch warning:
WARNING: function definition argument 'struct altera_cvp_conf *'

Signed-off-by: Carlos A Petry &lt;capetry.dev@gmail.com&gt;
Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285</title>
<updated>2019-06-05T15:36:37+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-29T14:17:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=8e8e69d67e5fad1a1edf97acebd649a6c8f1febd'/>
<id>8e8e69d67e5fad1a1edf97acebd649a6c8f1febd</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation version 2 of the license this program
  is distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 100 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Alexios Zavras &lt;alexios.zavras@intel.com&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.918357685@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation version 2 of the license this program
  is distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 100 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Alexios Zavras &lt;alexios.zavras@intel.com&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.918357685@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
