linux-toradex.git/drivers/fpga, branch v4.10

fpga: Clarify how write_init works streaming modes

2016-11-29T21:51:49+00:00

This interface was designed for streaming, but write_init's buf
argument has an unclear purpose. Define it to be the first bytes
of the bitstream. Each driver gets to set how many bytes (at most)
it wants to see. Short bitstreams will be passed through as-is, while
long ones will be truncated.

The intent is to allow drivers to peek at the header before the transfer
actually starts.

Signed-off-by: Jason Gunthorpe 
Acked-by: Alan Tull

fpga zynq: Fix incorrect ISR state on bootup

2016-11-29T21:51:48+00:00

It is best practice to clear and mask all interrupts before
associating the IRQ, and this should be done after the clock
is enabled.

This corrects a bad result from zynq_fpga_ops_state on bootup
where left over latched values in INT_STS_OFFSET caused it to
report an unconfigured FPGA as configured.

After this change the boot up operating state for an unconfigured
FPGA reports 'unknown'.

Signed-off-by: Jason Gunthorpe 
Acked-by: Alan Tull 
Acked-by: Moritz Fischer

fpga zynq: Remove priv->dev

2016-11-29T21:51:46+00:00

socfpga uses mgr->dev for debug prints, there should be consistency
here, so standardize on that. The only other use was for dma
which can be replaced with mgr->dev.parent.

Signed-off-by: Jason Gunthorpe 
Acked-by: Alan Tull 
Acked-by: Moritz Fischer

fpga zynq: Add missing \n to messages

2016-11-29T21:51:45+00:00

Function dev_err doesn't add a newline at the end of the string. This will
lead to a hard to read kernel log.

Signed-off-by: Jason Gunthorpe 
Reviewed-by: Moritz Fischer 
Reviewed-by: Matthias Brugger 
Acked-by: Alan Tull

fpga: Add COMPILE_TEST to all drivers

2016-11-29T21:51:44+00:00

Like Zynq the Altera drivers compile fine on x86 and others too,
so make it easier to compile test this stuff.

A10 requires REGMAP_MMIO to compile, so be explicit rather than
relying on it via ARCH_SOCFPGA.

Signed-off-by: Jason Gunthorpe 
Acked-by: Alan Tull

ARM: socfpga: checking the wrong variable

2016-11-17T07:14:55+00:00

This is a cut and paste bug.  We had intended to check "sysmgr".

Fixes: e5f8efa5c8bf ("ARM: socfpga: fpga bridge driver support")
Signed-off-by: Dan Carpenter 
Acked-by: Moritz Fischer 
Acked-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman

fpga-manager: Add Socfpga Arria10 support

2016-11-10T16:03:36+00:00

Add low level driver to support reprogramming FPGAs for Altera
SoCFPGA Arria10.

Signed-off-by: Alan Tull 
Reviewed-by: Moritz Fischer 
Signed-off-by: Greg Kroah-Hartman

fpga: add altera freeze bridge support

2016-11-10T16:03:36+00:00

Add a low level driver for Altera Freeze Bridges to the FPGA Bridge
framework.  A freeze bridge is a bridge that exists in the FPGA
fabric to isolate one region of the FPGA from the busses while that
one region is being reprogrammed.

Signed-off-by: Alan Tull 
Signed-off-by: Matthew Gerlach 
Signed-off-by: Greg Kroah-Hartman

ARM: socfpga: fpga bridge driver support

2016-11-10T16:03:36+00:00

Supports Altera SOCFPGA bridges:
 * fpga2sdram
 * fpga2hps
 * hps2fpga
 * lwhps2fpga

Allows enabling/disabling the bridges through the FPGA
Bridge Framework API functions.

The fpga2sdram driver only supports enabling and disabling
of the ports that been configured early on.  This is due to
a hardware limitation where the read, write, and command
ports on the fpga2sdram bridge can only be reconfigured
while there are no transactions to the sdram, i.e. when
running out of OCRAM before the kernel boots.

Device tree property 'init-val' configures the driver to
enable or disable the bridge during probe.  If the property
does not exist, the driver will leave the bridge in its
current state.

Signed-off-by: Alan Tull 
Signed-off-by: Matthew Gerlach 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Greg Kroah-Hartman

fpga: fpga-region: device tree control for FPGA

2016-11-10T16:03:35+00:00

FPGA Regions support programming FPGA under control of the Device
Tree.

Signed-off-by: Alan Tull 
Signed-off-by: Greg Kroah-Hartman