linux-toradex.git/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h, branch v5.3-rc3 Linux kernel for Apalis and Colibri modules drm/amdgpu: program for resuming preempted ib 2019-06-21T23:57:40+00:00 Jack Xiao Jack.Xiao@amd.com 2019-01-08T07:28:52+00:00 43974dacb6c35ea6a2bf89c1d5e2e04195464f81 For new submission ib, CE/DE metadata should be programmed to 0; for partially execution ib, CE/DE metadata should be restored. Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
For new submission ib, CE/DE metadata should be programmed to 0;
for partially execution ib, CE/DE metadata should be restored.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: init vega10 SR-IOV reg access mode 2019-05-24T17:20:50+00:00 Trigger Huang Trigger.Huang@amd.com 2019-05-09T09:32:59+00:00 78d481126795e9e4740204df95572d9731a6d34e Set different register access mode according to the features provided by firmware Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Set different register access mode according to the features
provided by firmware

Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: support dpm level modification under virtualization v3 2019-04-10T18:53:27+00:00 Yintian Tao yttao@amd.com 2019-04-09T12:33:20+00:00 bb5a2bdf36a8df79e1437b443299b7fe1ea3abfc Under vega10 virtualuzation, smu ip block will not be added. Therefore, we need add pp clk query and force dpm level function at amdgpu_virt_ops to support the feature. v2: add get_pp_clk existence check and use kzalloc to allocate buf v3: return -ENOMEM for allocation failure and correct the coding style Signed-off-by: Yintian Tao <yttao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Under vega10 virtualuzation, smu ip block will not be added.
Therefore, we need add pp clk query and force dpm level function
at amdgpu_virt_ops to support the feature.

v2: add get_pp_clk existence check and use kzalloc to allocate buf

v3: return -ENOMEM for allocation failure and correct the coding style

Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu/sriov: Aligned the definition with libgv 2018-11-19T20:27:42+00:00 Emily Deng Emily.Deng@amd.com 2018-11-14T15:20:13+00:00 bed1ed366d5f68a9e038364ec22fe34ed361c1ba Aligned the amd_sriov_msg_pf2vf_info_header and amd_sriov_msg_pf2vf_info_header's definition with libgv. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Frank.Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Aligned the amd_sriov_msg_pf2vf_info_header and amd_sriov_msg_pf2vf_info_header's
definition with libgv.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Frank.Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: cleanup GMC v9 TLB invalidation 2018-11-05T20:49:40+00:00 Christian König christian.koenig@amd.com 2018-10-25T08:49:07+00:00 af5fe1e96aa156886f89282371fce1629fcc9f6a Move the kiq handling into amdgpu_virt.c and drop the fallback. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Move the kiq handling into amdgpu_virt.c and drop the fallback.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Move csa related code to separate file 2018-11-05T19:21:49+00:00 Rex Zhu Rex.Zhu@amd.com 2018-10-19T05:35:48+00:00 7946340fa38965705f79273cef0cdc477239bf2d In baremetal, also need to reserve csa for preemption. so move the csa related code out of sriov. Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
In baremetal, also need to reserve csa for preemption.
so move the csa related code out of sriov.

Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Refine CSA related functions 2018-11-05T19:21:48+00:00 Rex Zhu Rex.Zhu@amd.com 2018-10-15T09:08:38+00:00 1e256e2762211c02078c31f839a9b243f62efd5e There is no functional changes, Use function arguments for SRIOV special variables which is hardcode in those functions. so we can share those functions in baremetal. Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
There is no functional changes,
Use function arguments for SRIOV special variables which
is hardcode in those functions.

so we can share those functions in baremetal.

Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Remove useless csa gpu address in vmid0 2018-11-05T19:21:48+00:00 Rex Zhu Rex.Zhu@amd.com 2018-10-16T08:27:53+00:00 20bedfe0c13a2e221301e3c889b2a4c48374f78a driver didn't use this address so far. Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
driver didn't use this address so far.

Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: move static CSA address to top of address space v2 2018-02-19T19:18:48+00:00 Christian König christian.koenig@amd.com 2018-01-22T10:25:48+00:00 6f05c4e9d1a1a743eca76ddbad788386d7bb534e Move the CSA area to the top of the VA space to avoid clashing with HMM/ATC in the lower range on GFX9. v2: wrong sign noticed by Roger, rebase on CSA_VADDR cleanup, handle VA hole on GFX9 as well. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Move the CSA area to the top of the VA space to avoid clashing with
HMM/ATC in the lower range on GFX9.

v2: wrong sign noticed by Roger, rebase on CSA_VADDR cleanup, handle VA
hole on GFX9 as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu:free CSA in unified place 2017-12-06T17:47:51+00:00 Monk Liu Monk.Liu@amd.com 2017-11-14T08:52:14+00:00 84e5b5161e7159bcf24dfeed9f985bd86e354ea8 instead of doing it in each GFX ip's sw_fini Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
instead of doing it in each GFX ip's sw_fini

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>