linux-toradex.git/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h, branch v5.3-rc3 Linux kernel for Apalis and Colibri modules drm/amdgpu: refine the PTE encoding of PRT for navi10 2019-06-21T02:35:29+00:00 Jack Xiao Jack.Xiao@amd.com 2019-02-22T07:34:00+00:00 7f95167ce131674ab77b46e4064f053e6c6f1552 Due to GCR change from navi10, the PTE encoding of PRT needs change VSCTL = 01111 (was 0XX1X). Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Due to GCR change from navi10, the PTE encoding of PRT
needs change VSCTL = 01111 (was 0XX1X).

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10 2019-06-21T02:35:29+00:00 Hawking Zhang Hawking.Zhang@amd.com 2018-06-25T13:03:40+00:00 7596ab68ff7dc13515f0c9dc3803472d75055c60 To differentiate the mtypes across asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
To differentiate the mtypes across asics.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: correct pte mtype field for navi 2019-06-21T02:35:29+00:00 Hawking Zhang Hawking.Zhang@amd.com 2019-04-12T23:17:24+00:00 c304b9e51914d6ffe765f35eb39310d35f988a28 The MTYPE filed moves from bits 58:57 to 50:48 for NV10 And the size of MTYPE field is now 3bits Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: provide the page fault queue to the VM code 2019-04-03T15:00:30+00:00 Christian König christian.koenig@amd.com 2019-03-25T15:13:44+00:00 c4229c6e37c203fd99397c1bcfe83a2bc1d30d96 We are going to need that for recoverable page faults. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
We are going to need that for recoverable page faults.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: drop the ib from the VM update parameters 2019-03-28T03:40:57+00:00 Christian König christian.koenig@amd.com 2019-03-21T15:43:39+00:00 110aef572afccc8d18c8d1ad6cb027795ec01cda It is redundant with the job pointer. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
It is redundant with the job pointer.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: move VM table mapping into the backend as well 2019-03-28T03:40:50+00:00 Christian König christian.koenig@amd.com 2019-03-21T15:34:18+00:00 ecf96b52bf98a22f14bd33c7deee0aad8eb6b569 Clean that up further and also fix another case where the BO wasn't kmapped for CPU based updates. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Clean that up further and also fix another case where the BO
wasn't kmapped for CPU based updates.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: XGMI pstate switch initial support 2019-03-28T03:40:43+00:00 shaoyunl shaoyun.liu@amd.com 2019-03-20T20:14:56+00:00 df399b064118bf9a5b9a3faaa67feb1cbb34e9d4 Driver vote low to high pstate switch whenever there is an outstanding XGMI mapping request. Driver vote high to low pstate when all the outstanding XGMI mapping is terminated. Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: use the new VM backend for PTEs 2019-03-21T18:59:28+00:00 Christian König christian.koenig@amd.com 2019-03-18T19:19:36+00:00 c3546695830e7d919f8aadba2c64807c40dad02b And remove the existing code when it is unused. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
And remove the existing code when it is unused.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: new VM update backends 2019-03-21T18:59:15+00:00 Christian König christian.koenig@amd.com 2019-03-18T12:16:03+00:00 6dd09027a22ac78f6ab1881aa7e2e21ad61c02b8 Separate out all functions for SDMA and CPU based page table updates into separate backends. This way we can keep most of the complexity of those from the core VM code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Separate out all functions for SDMA and CPU based page table
updates into separate backends.

This way we can keep most of the complexity of those from the
core VM code.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: move and rename amdgpu_pte_update_params 2019-03-21T18:59:00+00:00 Christian König christian.koenig@amd.com 2019-03-18T11:27:35+00:00 d1e29462a06ac3d11645b7d939b00bcf51b10cc3 Move the update parameter into the VM header and rename them. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Move the update parameter into the VM header and rename them.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>