linux-toradex.git/drivers/gpu/drm/amd/display/dc/dml, branch v5.8

drm/amd/display: Remove dml_common_def file

2020-05-21T16:48:43+00:00

During the rework for removing the FPU issues, I found the following
warning:

 [..] dml_common_defs.o: warning: objtool: dml_round()+0x9: FPU
      instruction outside of kernel_fpu_{begin,end}()

This file has a single function that does not need to be in a specific
file. This commit drop dml_common_defs file, and move dml_round function
to dml_inline_defs.

CC: Christian König 
CC: Alexander Deucher 
CC: Peter Zijlstra 
CC: Tony Cheng 
CC: Harry Wentland 
Signed-off-by: Rodrigo Siqueira 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: temporary clamp the vratio used to 1.0

2020-05-05T17:11:36+00:00

[Why]
in Is_Support function, driver report different caps between
same timing but different scaling cause OS inconsistent.

[How]
min_row_time is a local that’s only used for verifying immediate
flip support. Clamp the vratio used for its calculation to 1.0.

Signed-off-by: Lewis Huang 
Reviewed-by: Tony Cheng 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Allow PState switch in VBLANK one display VACTIVE

2020-05-05T17:11:23+00:00

[Why]
For certain display configurations we want to allow PSTATE
switch when one display can switch in VACTIVE and the
other display can switch in VBLANK

[How]
Add extra condition to dcn2 pstate support check

Signed-off-by: Alvin Lee 
Reviewed-by: Jun Lei 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Update DCN2.1 DV Code Revision

2020-05-05T17:10:52+00:00

[WHY & HOW]
There is a problem in hscale_pixel_rate, the bug
causes DCN to be more optimistic (more likely to underflow)
in upscale cases during prefetch.
This commit ports the fix from DV code to address these issues.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Add DML variable for future asics

2020-04-28T20:17:36+00:00

Signed-off-by: Joshua Aberback 
Reviewed-by: Dmytro Laktyushkin 
Reviewed-by: Jun Lei 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1

2020-04-22T22:11:48+00:00

[WHY]
In certain conditions with low pixel clock, some values in DML may go
past the max due to margining for latency hiding. This causes assertions
to get hit.

[HOW]
If the pixel clock is low and some values are high, cap it to the max.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Cast int to float before division

2020-04-22T22:11:47+00:00

[Why]:
Some inputs to dml_ceil have it dividied by int which causes a
truncation. This loss of precision means the ceil function becomes
redundant and does not round up.

[How]:
Cast parameter to float before division.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Set meta_chunk_value to 0 in DML if DCC disabled in DCN2.1

2020-04-22T22:11:47+00:00

[WHY]:
Calculating refcyc_per_meta_chunk_vblank_l when DCC is disabled may lead
to a large number causing an assert to get hit. In VBA, this value is 0
when DCC is disabled.

[HOW]:
Set value to 0 to avoid hitting the assert.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Update DRAM watermark before checking to update TTU

2020-04-09T14:43:17+00:00

[Why]
In most cases, DRAM watermark is large enough that the result of the
condition to increase TTU doesn't change after DRAM watermark is
increased. However, there is are cases where the condition fails and
becomes true after DRAM watermark is increased. This results in minTTU <
DRAM watermarks which leads to PSR hang since p-state is requested but
not allowed.

[How]
Check whether to update TTU after DRAM watermark is updated.

Signed-off-by: Jaehyun Chung 
Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Fix dcn21 num_states

2020-03-31T16:26:15+00:00

[Why]
DML expects num_states to exclude the duplicate state.

[How]
Set num_states to correct value to prevent array off-by-one error.  Also
refactor max clock level code for diags.

Signed-off-by: Dmytro Laktyushkin 
Signed-off-by: George Shen 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher