<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/gpu/drm/amd/display/dc/hwss/dcn314, branch master</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>drm/amd/display: Fixed Silence complier warnings in dc</title>
<updated>2026-03-30T19:12:15+00:00</updated>
<author>
<name>Gaghik Khachatrian</name>
<email>gaghik.khachatrian@amd.com</email>
</author>
<published>2026-03-09T21:18:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f82480fafedf622541276d48a3b4fed20ce5d866'/>
<id>f82480fafedf622541276d48a3b4fed20ce5d866</id>
<content type='text'>
[Why]
Resolve compiler warnings by marking unused parameters explicitly.

[How]
In .c and .h function definitions, keep parameter names
in signatures and add a line with `(void)param;` in function body

Preserved function signatures and avoids breaking code paths that
may reference the parameter under conditional compilation.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Reviewed-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Gaghik Khachatrian &lt;gaghik.khachatrian@amd.com&gt;
Signed-off-by: Chuanyu Tseng &lt;chuanyu.tseng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why]
Resolve compiler warnings by marking unused parameters explicitly.

[How]
In .c and .h function definitions, keep parameter names
in signatures and add a line with `(void)param;` in function body

Preserved function signatures and avoids breaking code paths that
may reference the parameter under conditional compilation.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Reviewed-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Gaghik Khachatrian &lt;gaghik.khachatrian@amd.com&gt;
Signed-off-by: Chuanyu Tseng &lt;chuanyu.tseng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Remove unused code</title>
<updated>2026-01-20T22:25:20+00:00</updated>
<author>
<name>Charlene Liu</name>
<email>Charlene.Liu@amd.com</email>
</author>
<published>2026-01-06T15:41:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c0d6f52f9b62479d61f8cd4faf9fb2f8bce6e301'/>
<id>c0d6f52f9b62479d61f8cd4faf9fb2f8bce6e301</id>
<content type='text'>
[why]
two sets of dccg_init:
one in dc/dccg, one in dc/hwss.
remove hwss's dccg_init for asics not use it.

Reviewed-by: Chris Park &lt;chris.park@amd.com&gt;
Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: Ilya Bakoulin &lt;Ilya.Bakoulin@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;matthew.stewart2@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[why]
two sets of dccg_init:
one in dc/dccg, one in dc/hwss.
remove hwss's dccg_init for asics not use it.

Reviewed-by: Chris Park &lt;chris.park@amd.com&gt;
Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: Ilya Bakoulin &lt;Ilya.Bakoulin@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;matthew.stewart2@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Correct DSC padding accounting</title>
<updated>2025-12-08T18:56:37+00:00</updated>
<author>
<name>Relja Vojvodic</name>
<email>rvojvodi@amd.com</email>
</author>
<published>2025-11-12T20:21:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c7062be3380cb20c8b1c4a935a13f1848ead0719'/>
<id>c7062be3380cb20c8b1c4a935a13f1848ead0719</id>
<content type='text'>
[WHY]
- After the addition of all OVT patches, DSC padding was being accounted
  for multiple times, effectively doubling the padding
- This caused compliance failures or corruption

[HOW]
- Add padding to DSC pic width when required by HW, and do not re-add
  when calculating reg values
- Do not add padding when computing PPS values, and instead track padding
  separately to add when calculating slice width values

Reviewed-by: Chris Park &lt;chris.park@amd.com&gt;
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Relja Vojvodic &lt;rvojvodi@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY]
- After the addition of all OVT patches, DSC padding was being accounted
  for multiple times, effectively doubling the padding
- This caused compliance failures or corruption

[HOW]
- Add padding to DSC pic width when required by HW, and do not re-add
  when calculating reg values
- Do not add padding when computing PPS values, and instead track padding
  separately to add when calculating slice width values

Reviewed-by: Chris Park &lt;chris.park@amd.com&gt;
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Relja Vojvodic &lt;rvojvodi@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Correct slice width calculation for YCbCr420</title>
<updated>2025-10-13T18:14:31+00:00</updated>
<author>
<name>Relja Vojvodic</name>
<email>rvojvodi@amd.com</email>
</author>
<published>2025-09-17T16:30:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=81557c96c8a171b5d2500662d4d62f27ab6bad23'/>
<id>81557c96c8a171b5d2500662d4d62f27ab6bad23</id>
<content type='text'>
[Why]
-OVT compliance testing for 5120x2880p300Hz YCbCr420 was failing due to
incorrect slice width being calculated

[How]
-Ensure slice width is divisible by 2 for 420 to comply with spec

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Relja Vojvodic &lt;rvojvodi@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why]
-OVT compliance testing for 5120x2880p300Hz YCbCr420 was failing due to
incorrect slice width being calculated

[How]
-Ensure slice width is divisible by 2 for 420 to comply with spec

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Relja Vojvodic &lt;rvojvodi@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Rename header file link.h to link_service.h</title>
<updated>2025-09-15T20:57:29+00:00</updated>
<author>
<name>Wesley Chalmers</name>
<email>Wesley.Chalmers@amd.com</email>
</author>
<published>2025-09-03T01:47:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=782f0bb5a129f588dc16ad54a2e88c93ef2e079a'/>
<id>782f0bb5a129f588dc16ad54a2e88c93ef2e079a</id>
<content type='text'>
[WHY]
Header file name "link.h" collides with system header when dc is
compiled as a user-mode library

[WHAT]
Rename link.h to link_service.h to avoid name collision

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY]
Header file name "link.h" collides with system header when dc is
compiled as a user-mode library

[WHAT]
Rename link.h to link_service.h to avoid name collision

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Clear the CUR_ENABLE register on DCN314 w/out DPP PG</title>
<updated>2025-08-29T14:22:52+00:00</updated>
<author>
<name>Ivan Lipski</name>
<email>ivan.lipski@amd.com</email>
</author>
<published>2025-08-20T19:46:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=645f74f1dc119dad5a2c7bbc05cc315e76883011'/>
<id>645f74f1dc119dad5a2c7bbc05cc315e76883011</id>
<content type='text'>
[Why&amp;How]
ON DCN314, clearing DPP SW structure without power gating it can cause a
double cursor in full screen with non-native scaling.

A W/A that clears CURSOR0_CONTROL cursor_enable flag if
dcn10_plane_atomic_power_down is called and DPP power gating is disabled.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4168
Reviewed-by: Sun peng (Leo) Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why&amp;How]
ON DCN314, clearing DPP SW structure without power gating it can cause a
double cursor in full screen with non-native scaling.

A W/A that clears CURSOR0_CONTROL cursor_enable flag if
dcn10_plane_atomic_power_down is called and DPP power gating is disabled.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4168
Reviewed-by: Sun peng (Leo) Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Adding interface to log hw state when underflow happens</title>
<updated>2025-08-04T18:40:32+00:00</updated>
<author>
<name>Muhammad Ahmed</name>
<email>Muhammad.Ahmed@amd.com</email>
</author>
<published>2025-07-25T01:50:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=5dc0ec782ef17ed10b87fa0962388040a86602c8'/>
<id>5dc0ec782ef17ed10b87fa0962388040a86602c8</id>
<content type='text'>
[why]
Will help us better debug underflow issues.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Muhammad Ahmed &lt;Muhammad.Ahmed@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[why]
Will help us better debug underflow issues.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Muhammad Ahmed &lt;Muhammad.Ahmed@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Revert "Add DPP &amp; HUBP reset if power gate enabled on DCN314"</title>
<updated>2025-07-15T18:07:53+00:00</updated>
<author>
<name>Ivan Lipski</name>
<email>ivan.lipski@amd.com</email>
</author>
<published>2025-07-02T19:34:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=ad19aa07445c2313c996040408a18b75db8f604c'/>
<id>ad19aa07445c2313c996040408a18b75db8f604c</id>
<content type='text'>
This reverts commit 99e25e4683d7cfdf79dcc328e11bb6c924c77566.

[Why &amp; How]
This commit caused a blank screen on internal display when projecting to
an external display on DCN314.

Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 99e25e4683d7cfdf79dcc328e11bb6c924c77566.

[Why &amp; How]
This commit caused a blank screen on internal display when projecting to
an external display on DCN314.

Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Add DPP &amp; HUBP reset if power gate enabled on DCN314</title>
<updated>2025-06-30T15:59:29+00:00</updated>
<author>
<name>Ivan Lipski</name>
<email>ivlipski@amd.com</email>
</author>
<published>2025-06-19T22:14:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=99e25e4683d7cfdf79dcc328e11bb6c924c77566'/>
<id>99e25e4683d7cfdf79dcc328e11bb6c924c77566</id>
<content type='text'>
[WHY]
On DCN314, using full screen application with enabled scaling like 150%,
175%, with overlay cursor, causes a second cursor to appear when changing
planes. Dpp cache is used to track the HW cursor enable. Since power gate
is disabled for hubp &amp; dpp in DCN314, dpp_reset() zero'ed the dpp struct,
while the dpp hardware was not power gated.

So, when plane is changed in a full screen app, and the overlay cursor is
enabled, the cache is cleared, so the cache does not represent the actual
cursor state.

[HOW]
Added conditionals for dpp &amp; hubp reset and their pg_control functions
only if according power_gate flags are enabled.

Reviewed-by: Sun peng Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivlipski@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY]
On DCN314, using full screen application with enabled scaling like 150%,
175%, with overlay cursor, causes a second cursor to appear when changing
planes. Dpp cache is used to track the HW cursor enable. Since power gate
is disabled for hubp &amp; dpp in DCN314, dpp_reset() zero'ed the dpp struct,
while the dpp hardware was not power gated.

So, when plane is changed in a full screen app, and the overlay cursor is
enabled, the cache is cleared, so the cache does not represent the actual
cursor state.

[HOW]
Added conditionals for dpp &amp; hubp reset and their pg_control functions
only if according power_gate flags are enabled.

Reviewed-by: Sun peng Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivlipski@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Skip to enable dsc if it has been off</title>
<updated>2025-04-07T19:18:30+00:00</updated>
<author>
<name>Paul Hsieh</name>
<email>Paul.Hsieh@amd.com</email>
</author>
<published>2025-03-11T09:16:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=8b8a602c985e99074fa1d5233cd224b7bcfb9df2'/>
<id>8b8a602c985e99074fa1d5233cd224b7bcfb9df2</id>
<content type='text'>
[Why]
It makes DSC enable when we commit the stream which need
keep power off.And then it will skip to disable DSC if
pipe reset at this situation as power has been off. It may
cause the DSC unexpected enable on the pipe with the
next new stream which doesn't support DSC.

[HOW]
Check the DSC used on current pipe status when update stream.
Skip to enable if it has been off. The operation enable
DSC should happen when set power on.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Paul Hsieh &lt;Paul.Hsieh@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why]
It makes DSC enable when we commit the stream which need
keep power off.And then it will skip to disable DSC if
pipe reset at this situation as power has been off. It may
cause the DSC unexpected enable on the pipe with the
next new stream which doesn't support DSC.

[HOW]
Check the DSC used on current pipe status when update stream.
Skip to enable if it has been off. The operation enable
DSC should happen when set power on.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Paul Hsieh &lt;Paul.Hsieh@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
