linux-toradex.git/drivers/gpu/drm/amd/display/dmub/src, branch master

drm/amd/display: Enable bootcrc on FW side

2026-01-27T23:10:38+00:00

[Why]
The bootcrc feature is controlled on the FW side.

[How]
Pass the control bits in boot options to FW.

Reviewed-by: ChiaHsuan (Tom) Chung 
Signed-off-by: Wayne Lin 
Signed-off-by: Aurabindo Pillai 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add new fields to fams2 config

2026-01-05T21:59:59+00:00

[WHY&HOW]
Adds new fields to the fams2 configuration structure.

Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Dillon Varone 
Signed-off-by: Chenyu Chen 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Consolidate dmub fb info to a single struct

2026-01-05T21:59:59+00:00

[WHY&HOW]
Consolidate dmub fb info into a single structure to simplify translation
between components.

Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Dillon Varone 
Signed-off-by: Chenyu Chen 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add additional checks for PSP footer size

2025-12-08T18:56:37+00:00

[WHY & HOW]
Newer ASICs have different PSP footer sizes which lead to driver
failing to locate the DMCUB FW meta info, which in turn causes
improper DMCUB FW loading and causes DMCUB to crash.

Add support for custom PSP footer sizes and check 512B by default
as well.

Reviewed-by: Charlene Liu 
Signed-off-by: Ovidiu Bunea 
Signed-off-by: Alex Hung 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Increase IB mem size

2025-11-04T16:53:20+00:00

[Why & How]
Increase IB mem size to match size of largest structure that will
use IB transfer between driver and DMU.

Reviewed-by: Oleh Kuzhylnyi 
Signed-off-by: Alvin Lee 
Signed-off-by: Ray Wu 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add dc interface to log pre os firmware information

2025-10-28T13:58:11+00:00

[Why]
Pre os firmware information is useful to debug pre os to post os fw
transition issues.

[How]
Add dc interface dc_log_preos_dmcub_info() to log pre os firmware
information.

Reviewed-by: Cruise Hung 
Signed-off-by: Meenakshikumar Somasundaram 
Signed-off-by: Wayne Lin 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix DMUB reset sequence for DCN32

2025-10-28T13:57:21+00:00

[WHY&HOW]
Backport reset sequence fixes implemented on DCN401 to DCN32 to address
stability issues when resetting the DMUB.

Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Dillon Varone 
Signed-off-by: Wayne Lin 
Tested-by: Dan Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Control BW allocation in FW side

2025-10-20T22:26:33+00:00

[Why]
The BW allocation feature should be controlled in FW side.

[How]
Pass the control bit to FW boot option.

Reviewed-by: Meenakshikumar Somasundaram 
Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Cruise Hung 
Signed-off-by: Tom Chung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Driver implementation for cursor offloading to DMU

2025-10-13T18:14:32+00:00

[Why]
We require an interlock between driver and firmware for upcoming
features and given that this could possibly happen on any single
cursor programming call (and that we can't asynchronously wait for
firmware to respond because of it) we'd be regressing cursor performance
by at least an extra 40us per call.

When we could possibly have cursor update every 20us - 100s from high
frequency gaming mice this means that we'd be stuttering or dropping
updates and impacting overall cursor performance.

We want a solution that can:

1. Interlock between other firmware features
2. Not stall out or require the DMCUB lock for every single update

[How]
When cursor offloading is enabled and supported by an ASIC driver will
route the cursor programming through to DMU as part of the regular
DC stream cursor programming interfaces for attributes and position.

The atomic pipe programming version will not be updated: this will still
follow the existing programming path by keeping track of a field that
specifies when the register writes should be deferred to DMU.

Cursor locking is not required when cursor offload is in progress since
the updates are consolidated and processed by DMU once at the end
of the frame in a periodic manner.

The shared buffer the firmware queries from is allocated along with the
rest of the scratch state region in an area that's accessible by
both firmware and driver.

The size of the cursor offload (v1) state will not change, but it does
have a unique union per ASIC version with room for expansion if needed.

When firmware features notifying DMU of DRR updates are not enabled we
now send an explicit vtotal min/max update via driver to DMU firmware
whenever the vtotal max changes. This is to allow the cursor programming
to determine the appropriate latch update point offset from vupdate.

Reviewed-by: Dillon Varone 
Signed-off-by: Nicholas Kazlauskas 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher

drm/amd/display: Fix DMCUB loading sequence for DCN3.2

2025-09-15T20:57:21+00:00

[Why]
New sequence from HW for reset and firmware reloading has been
provided that aims to stabilize the reload sequence in the case the
firmware is hung or has outstanding requests.

[How]
Update the sequence to remove the DMUIF reset and the redundant
writes in the release.

Reviewed-by: Sreeja Golui 
Signed-off-by: Nicholas Kazlauskas 
Signed-off-by: Ray Wu 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher