linux-toradex.git/drivers/gpu/drm/amd/display/include, branch v6.10 Linux kernel for Apalis and Colibri modules drm/amd/display: Send DP_TOTAL_LTTPR_CNT during detection if LTTPR is present 2024-06-25T18:15:45+00:00 Michael Strauss michael.strauss@amd.com 2023-11-28T15:31:12+00:00 2ec6c7f802332d1eff16f03e7c757f1543ee1183 [WHY] New register field added in DP2.1 SCR, needed for auxless ALPM [HOW] Echo value read from 0xF0007 back to sink Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[WHY]
New register field added in DP2.1 SCR, needed for auxless ALPM

[HOW]
Echo value read from 0xF0007 back to sink

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove redundant include file 2024-04-26T21:22:44+00:00 Alex Hung alex.hung@amd.com 2024-04-15T19:47:37+00:00 e0dd5782f8393d3c7e5f2fdab81c709088dd4368 This fixes 1 PW.INCLUDE_RECURSION reported by Coverity. "./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h" includes itself: dc_types.h -> dal_types.h -> dc_types.h Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This fixes 1 PW.INCLUDE_RECURSION reported by Coverity.

"./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h"
includes itself: dc_types.h -> dal_types.h -> dc_types.h

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add a function for checking tmds mode 2024-04-12T04:36:47+00:00 Chris Park chris.park@amd.com 2024-04-02T06:06:00+00:00 ab956ed95b8bc4a65c913d7057075866d5fc3724 [Why] DVI is TMDS signal like HDMI but without audio. Current signal check does not correctly reflect DVI clock programming. [How] Define a new signal check for TMDS that includes DVI to HDMI TMDS programming. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why]
DVI is TMDS signal like HDMI but without audio.  Current signal check
does not correctly reflect DVI clock programming.

[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix compiler redefinition warnings for certain configs 2024-04-10T01:51:11+00:00 Mounika Adhuri moadhuri@amd.com 2024-03-15T16:06:10+00:00 fec85f995a4ba43d1a1359934c7fe577389c300d [why & how] Modified definitions of 1 function and 2 structs to remove warnings on certain specific compiler configurations due to redefinition. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Mounika Adhuri <moadhuri@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[why & how]
Modified definitions of 1 function and 2 structs to remove warnings on
certain specific compiler configurations due to redefinition.

Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Mounika Adhuri <moadhuri@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add comments to v_total calculation and drop legacy TODO 2024-03-20T17:37:38+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-02-14T20:32:32+00:00 f1b8479dc997a0e625f3d94920cd778f55e299b5 [WHY & HOW] This commit just adds some simple comments to help understand the calculation of V total duration for Freesync. Also, remove a legacy TODO comment from link service type. Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[WHY & HOW]
This commit just adds some simple comments to help understand the
calculation of V total duration for Freesync. Also, remove a legacy TODO
comment from link service type.

Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add debug prints for IPS testing 2024-03-20T17:37:37+00:00 Nicholas Kazlauskas nicholas.kazlauskas@amd.com 2024-02-15T16:10:18+00:00 460ea5b3b61604171e6668ce1db2d640c4c8ae7f [WHY] To log commit states and when we transition in/out of allow and idle states and the caller. [HOW] Add a new logging helper and wrap idle optimization calls to receive the caller. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[WHY]
To log commit states and when we transition in/out of allow and idle
states and the caller.

[HOW]
Add a new logging helper and wrap idle optimization calls to receive
the caller.

Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: add DCN351 version identifiers 2024-03-04T20:59:07+00:00 Hamza Mahfooz hamza.mahfooz@amd.com 2024-02-16T20:02:21+00:00 1c1a92068d308ed56fac03af9c8149530cb6e973 Add DCN3.5.1 ASIC identifiers. Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add DCN3.5.1 ASIC identifiers.

Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Update FIXED_VS Retimer HWSS Test Pattern Sequences 2024-02-14T22:13:03+00:00 Michael Strauss michael.strauss@amd.com 2024-01-12T17:19:40+00:00 bb46122db730f42f3fc1d9d511b3d6ebe8375cdd [WHY] Need to fix some broken logic and sequencing in initial commit [HOW] Fix logic handling override deprogramming when exiting SQ128. Don't exit early from dp_set_hw_lane_settings for DP2/FIXED_VS case. Move LTTPR 128b/132b check out of requires_hwss and check during runtime, as LTTPR caps are not populated on initial call. Add pending_test_pattern to link state to allow HWSS to set FFE overrides on retimer TX and/or skip setting APU TX FFE depending on requested pattern. Use updated clock source for SQ128 override sequence. Skip HW FFE preset programming when performing test pattern overrides. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[WHY]
Need to fix some broken logic and sequencing in initial commit

[HOW]
Fix logic handling override deprogramming when exiting SQ128.

Don't exit early from dp_set_hw_lane_settings for DP2/FIXED_VS case.

Move LTTPR 128b/132b check out of  requires_hwss and check during
runtime, as LTTPR caps are not populated on initial call.

Add pending_test_pattern to link state to allow HWSS to set FFE overrides
on retimer TX and/or skip setting APU TX FFE depending on requested pattern.

Use updated clock source for SQ128 override sequence.

Skip HW FFE preset programming when performing test pattern overrides.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add DP audio BW validation 2024-01-15T23:35:39+00:00 George Shen george.shen@amd.com 2023-11-21T23:32:52+00:00 12f72a1599dc90b7f698b6a86a477ca4f2ef1f8e [Why] Timings with small HBlank (such as CVT RBv2) can result in insufficient HBlank bandwidth for audio SDP transmission when DSC is active. This will cause some higher bandwidth audio modes to fail. The combination of CVT RBv2 timings + DSC can commonly be encountered in MST scenarios. [How] Add DP audio bandwidth validation for 8b/10b MST and 128b/132b SST/MST cases and filter out modes that cannot be supported with the current timing config. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why]
Timings with small HBlank (such as CVT RBv2) can result in insufficient
HBlank bandwidth for audio SDP transmission when DSC is active. This
will cause some higher bandwidth audio modes to fail.

The combination of CVT RBv2 timings + DSC can commonly be encountered
in MST scenarios.

[How]
Add DP audio bandwidth validation for 8b/10b MST and 128b/132b SST/MST
cases and filter out modes that cannot be supported with the current
timing config.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: To adjust dprefclk by down spread percentage 2024-01-09T20:43:53+00:00 Martin Tsai martin.tsai@amd.com 2023-12-18T08:36:44+00:00 17e74e11ac2b46e7514705ae7abfb93ac0e20bd6 [Why] Panels show corruption with high refresh rate timings when ssc is enabled. [How] Read down-spread percentage from lut to adjust dprefclk. Issues come from S0i3 with this commit has been fixed by SMU. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Martin Tsai <martin.tsai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why]
Panels show corruption with high refresh rate timings when ssc is
enabled.

[How]
Read down-spread percentage from lut to adjust dprefclk. Issues come
from S0i3 with this commit has been fixed by SMU.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>