linux-toradex.git/drivers/gpu/drm/amd/include/v9_structs.h, branch v5.5-rc7 Linux kernel for Apalis and Colibri modules drm/amdkfd: Extend CU mask to 8 SEs (v3) 2019-08-02T15:19:11+00:00 Jay Cornwall Jay.Cornwall@amd.com 2019-07-18T21:57:22+00:00 5145d57ec5f5cf7dadaa6ccd9c9f1e4dae82570b Following bitmap layout logic introduced by: "drm/amdgpu: support get_cu_info for Arcturus". v2: squash in fixup for gfx_v9_0.c (Alex) v3: squash in debug print output fix Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Following bitmap layout logic introduced by:
"drm/amdgpu: support get_cu_info for Arcturus".

v2: squash in fixup for gfx_v9_0.c (Alex)
v3: squash in debug print output fix

Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdkfd: Shift sdma_engine_id and sdma_queue_id in mqd 2019-05-24T17:21:01+00:00 Oak Zeng ozeng@amd.com 2018-12-04T22:08:33+00:00 c6fd980ab154455df62adc89d81898d24654ab72 FW of some new ASICs requires sdma mqd size to be not more than 128 dwords. Repurpose the last 2 reserved fields of sdma mqd for driver internal use, so the total mqd size is no bigger than 128 dwords Signed-off-by: Oak Zeng <ozeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
FW of some new ASICs requires sdma mqd size to be not more than
128 dwords. Repurpose the last 2 reserved fields of sdma mqd for
driver internal use, so the total mqd size is no bigger than 128
dwords

Signed-off-by: Oak Zeng <ozeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Update GFXv9 SDMA MQD structure 2018-04-10T21:32:59+00:00 Felix Kuehling Felix.Kuehling@amd.com 2018-04-10T21:32:59+00:00 cf05fb8b144dae55d094b0fa7991e985a9b4561e This matches what the HWS firmware expects on GFXv9 chips. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> 
This matches what the HWS firmware expects on GFXv9 chips.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
drm/amdgpu/gfx9: adjust mqd allocation size 2017-08-29T19:28:00+00:00 Alex Deucher alexander.deucher@amd.com 2017-08-19T03:52:37+00:00 ffe6d881e99413f3ebdfebf99570c2e840879e68 To allocate additional space for the dynamic cu masks. Confirmed with the hw team that we only need 1 dword for the mask. The mask is the same for each SE so you only need 1 dword. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
To allocate additional space for the dynamic cu masks.
Confirmed with the hw team that we only need 1 dword
for the mask.  The mask is the same for each SE so
you only need 1 dword.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx9: update mqd to include dynamic CU mask 2017-08-29T19:27:59+00:00 Alex Deucher alexander.deucher@amd.com 2017-08-19T03:36:08+00:00 29696bd680f196f52c6d5eedc4da4ef0482d8bb9 Necessary for proper operation with KIQ. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Necessary for proper operation with KIQ.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx9: impl gfx9 meta data emit 2017-03-30T03:55:01+00:00 Xiangliang Yu Xiangliang.Yu@amd.com 2017-03-07T05:56:03+00:00 cca02cd3d40d11468f53c502c0579963b42d4f34 Insert ce meta prior to cntx_cntl and de follow it. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Insert ce meta prior to cntx_cntl and de follow it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add MQD structs for GFX V9 2017-03-30T03:54:29+00:00 Felix Kuehling Felix.Kuehling@amd.com 2017-03-02T21:57:08+00:00 4b219123e9edd8b99809e0c7c0eb201f6e6fc655 This header defines the gfx v9 MEC structures. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This header defines the gfx v9 MEC structures.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>