linux-toradex.git/drivers/gpu/drm/amd/include, branch v5.9-rc3 Linux kernel for Apalis and Colibri modules drm/amd/display: Read VBIOS Golden Settings Tbl 2020-08-06T20:47:13+00:00 Igor Kravchenko Igor.Kravchenko@amd.com 2020-07-20T00:45:28+00:00 098214999c8f8eea8dffddb61be5742fac2c829e [Why] For ver.4.4 and higher VBIOS contains default setting table. {How] Read Golden Settings Table from VBIOS, apply Aux tuning parameters. Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why]
For ver.4.4 and higher VBIOS contains default setting table.

{How]
Read Golden Settings Table from VBIOS, apply Aux tuning parameters.

Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/atomfirmware: update to latest integratedinfotable 2020-07-02T16:02:57+00:00 Alex Deucher alexander.deucher@amd.com 2020-06-25T21:46:46+00:00 2fde24e4dc8adc73ba69c5eea347822d5b8a2423 Used for renoir. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Used for renoir.

Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm amdgpu: SI UVD registers 2020-07-01T05:59:24+00:00 Sonny Jiang sonny.jiang@amd.com 2020-06-10T20:02:21+00:00 2282b4186dee80c89906d0ee10295393582c3afd Add SI UVD registers files. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add SI UVD registers files.

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2) 2020-07-01T05:59:22+00:00 Tom St Denis tom.stdenis@amd.com 2020-06-16T12:47:04+00:00 614c56111cc73f0a828634dcb2eecd2035c2104b Despite having different IP offsets the computed address of the register(s) are the same between gfx7..gfx10. This patch fixes the offset relative to the GC block on gfx10. (v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ... Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10.  This patch fixes the offset relative
to the GC block on gfx10.

(v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers 2020-07-01T05:59:21+00:00 Tom St Denis tom.stdenis@amd.com 2020-06-15T16:17:46+00:00 e3569fab49886123c81f18d675fb1719d73cf27d Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits 2020-07-01T05:59:19+00:00 Tom St Denis tom.stdenis@amd.com 2020-06-11T11:54:13+00:00 8d7fb7a10a825bd2e2c0fde7979cd8774c332bea Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.

Requested for UMR debugging.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2) 2020-07-01T05:59:19+00:00 Tom St Denis tom.stdenis@amd.com 2020-06-09T11:49:59+00:00 055e23e3d9ea1d680977f8e34f9678c17cb3cfc1 Requested for UMR support. (v2): Also add reg/bits for gfx9 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Requested for UMR support.

(v2): Also add reg/bits for gfx9 headers

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: and smc dpm info struct for sienna_cichlid 2020-07-01T05:59:13+00:00 Likun Gao Likun.Gao@amd.com 2020-04-17T18:03:19+00:00 44e7139b45a236fe0337b66fbfbdabce3a95dae0 And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add firmware_info v3_4 structure for Sienna_Cichlid 2020-07-01T05:59:10+00:00 Hawking Zhang Hawking.Zhang@amd.com 2020-01-22T20:08:59+00:00 718715e6a484c882a74f9f0e08b3d4c477cd70dd firmware_info v3_4 strucure will be used by kernel driver to query various parameters set by VBIOS for Sienna_Cichlid Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
firmware_info v3_4 strucure will be used by kernel driver
to query various parameters set by VBIOS for Sienna_Cichlid

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add vram_info v2_5 in atomfirmware header 2020-07-01T05:59:09+00:00 Hawking Zhang Hawking.Zhang@amd.com 2020-01-19T20:41:40+00:00 9d3708169f4494bdccc4f8b89a8f866767c563b7 vram_info v2_5 was introduced to support sienna_cichlid Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
vram_info v2_5 was introduced to support sienna_cichlid

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>