linux-toradex.git/drivers/gpu/drm/amd/include, branch v6.11-rc2 Linux kernel for Apalis and Colibri modules drm/amdgpu: increase mes log buffer size for gfx12 2024-07-27T22:10:12+00:00 Michael Chen michael.chen@amd.com 2024-07-23T21:45:23+00:00 9038e25c80558d48ce33d6d8c168666164dc72e9 MES firmware requires larger log buffer for gfx12. Allocate proper buffer respectively for gfx11 and gfx12. Signed-off-by: Michael Chen <michael.chen@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 739d0f3e1f36738d4cd84166784a8f7a58d69612) 
MES firmware requires larger log buffer for gfx12. Allocate
proper buffer respectively for gfx11 and gfx12.

Signed-off-by: Michael Chen <michael.chen@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 739d0f3e1f36738d4cd84166784a8f7a58d69612)
drm/amdgpu: Fix atomics on GFX12 2024-07-24T21:30:23+00:00 David Belanger david.belanger@amd.com 2024-06-10T20:38:55+00:00 73048bda46c3085df5fd42840de09523386d3e54 If PCIe supports atomics, configure register to prevent DF from breaking atomics in separate load/store operations. Signed-off-by: David Belanger <david.belanger@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 666f14cab21b17ccc1bdfe1e82458aa429b3b7e0) 
If PCIe supports atomics, configure register to prevent DF from
breaking atomics in separate load/store operations.

Signed-off-by: David Belanger <david.belanger@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 666f14cab21b17ccc1bdfe1e82458aa429b3b7e0)
drm/amdgpu/atomfirmware: silence UBSAN warning 2024-07-02T22:07:31+00:00 Alex Deucher alexander.deucher@amd.com 2024-07-01T16:50:10+00:00 4ed6a3689caba239e6df18c60af9489001f481c3 This is a variable sized array. Link: https://lists.freedesktop.org/archives/amd-gfx/2024-June/110420.html Tested-by: Jeff Layton <jlayton@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This is a variable sized array.

Link: https://lists.freedesktop.org/archives/amd-gfx/2024-June/110420.html
Tested-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Map ISP interrupts as generic IRQs 2024-06-27T21:34:40+00:00 Pratap Nirujogi pratap.nirujogi@amd.com 2024-05-08T02:49:46+00:00 0253d718a070ba109046299847fe8f3cf7568c3c Map ISP IH interrupts to Linux generic IRQ for ISP driver to handle the interrupts using MFD IORESOURCE_IRQ resource. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Map ISP IH interrupts to Linux generic IRQ for ISP driver to
handle the interrupts using MFD IORESOURCE_IRQ resource.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add ISP support to amdgpu_discovery 2024-06-27T21:34:39+00:00 Pratap Nirujogi pratap.nirujogi@amd.com 2024-05-02T20:51:39+00:00 772e4d56dab5448eb120f74811eaa71d7a474c1f ISP hw block is supported in some of the AMD GPU versions, add support to discover ISP IP in amdgpu_discovery. v2: squash in documentation update (Alex) Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
ISP hw block is supported in some of the AMD GPU versions, add support
to discover ISP IP in amdgpu_discovery.

v2: squash in documentation update (Alex)

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add some missing register definitions 2024-06-27T21:32:17+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2024-06-25T18:17:46+00:00 ad89e904e3aaa93628785546034ec77f3100cf79 Add some register offsets that are required for Display DCC on DCN401 Fixes: 2d072b445622 ("drm/amd: Add reg definitions for DCN401 DCC") Reported-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add some register offsets that are required for Display DCC on DCN401

Fixes: 2d072b445622 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add reg definitions for DCN401 DCC 2024-06-27T21:10:38+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2024-06-14T19:42:55+00:00 2d072b445622b90f8a961c0376887120da75221f [WHAT] Add the necessary register definitions to enable DCC on DCN4x Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[WHAT]
Add the necessary register definitions to enable DCC on DCN4x

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Update soc24_enum.h and soc21_enum.h 2024-06-05T15:25:14+00:00 Frank Min Frank.Min@amd.com 2024-05-27T05:22:16+00:00 3c7758beb269667373421fe7c7c44adcc7129d02 Update to latest changes. Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Update to latest changes.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update gc_12_0_0 headers 2024-06-05T15:03:10+00:00 Alex Deucher alexander.deucher@amd.com 2024-05-31T15:57:00+00:00 b592d01df6efa2a4a93e360358b1f45057c80dda Add some additional registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add some additional registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds 2024-06-05T15:02:24+00:00 Tasos Sahanidis tasos@tasossah.com 2024-05-31T16:23:30+00:00 98f9e5ea474d834eed2e1fb163ef3ab956ef8205 Flexible arrays used [1] instead of []. Replace the former with the latter to resolve multiple UBSAN warnings observed on boot with a BONAIRE card. In addition, use the __counted_by attribute where possible to hint the length of the arrays to the compiler and any sanitizers. Signed-off-by: Tasos Sahanidis <tasos@tasossah.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Flexible arrays used [1] instead of []. Replace the former with the latter
to resolve multiple UBSAN warnings observed on boot with a BONAIRE card.

In addition, use the __counted_by attribute where possible to hint the
length of the arrays to the compiler and any sanitizers.

Signed-off-by: Tasos Sahanidis <tasos@tasossah.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>