linux-toradex.git/drivers/gpu/drm/amd/include, branch v7.0-rc5 Linux kernel for Apalis and Colibri modules drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailbox 2026-03-04T18:15:00+00:00 sguttula suresh.guttula@amd.com 2026-02-25T08:27:01+00:00 a145bbff6f53ab80757a15eba5ad2ba8e3bdc9dc The reason the RAP is not granting access to 0x58200 is that a dedicated RSMU slot would have to be spent for this address range, and MPASP is close to running out of RSMU slots. This will help to fix PSP TOC load failure during secureboot. GFX Driver Need to use indirect access for SMN address regs. Signed-off-by: sguttula <suresh.guttula@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 9b822e26eea3899003aa8a89d5e2c4408e066e20) 
The reason the RAP is not granting access to 0x58200 is that
a dedicated RSMU slot would have to be spent for this address range,
and MPASP is close to running out of RSMU slots.

This will help to fix PSP TOC load failure during secureboot.
GFX Driver Need to use indirect access for SMN address regs.

Signed-off-by: sguttula <suresh.guttula@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 9b822e26eea3899003aa8a89d5e2c4408e066e20)
drm/amdgpu: Move xgmi status to interface header 2026-02-12T20:22:00+00:00 Lijo Lazar lijo.lazar@amd.com 2026-02-06T13:43:23+00:00 9aca641143cec1b25e76f54fc49187b17393c12f These definitions are used by user APIs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
These definitions are used by user APIs.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include : Update MES v12 API header - SUSPEND 2026-01-27T23:08:35+00:00 Shaoyun Liu shaoyun.liu@amd.com 2026-01-22T15:51:11+00:00 1bf8b4642c5f511dd73653a25ed7cd0470118389 Update SUSPEND API to support sdma queues. It's been supportted since 0x82 for gfx12 Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Update SUSPEND API to support sdma queues.
It's been supportted since 0x82 for gfx12

Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Enable SMU 15_0_0 support 2026-01-08T16:41:42+00:00 Pratik Vishwakarma Pratik.Vishwakarma@amd.com 2025-12-05T19:12:03+00:00 c7fc0f372374cf463be2ba4b5b21c20c3c051bb6 Add SMU 15_0_0 v2: rebase (Alex) v3: fix clang build (Alex) Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add SMU 15_0_0

v2: rebase (Alex)
v3: fix clang build (Alex)

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add THM 15.0.0 headers 2026-01-08T16:41:30+00:00 Alex Deucher alexander.deucher@amd.com 2025-12-05T15:58:52+00:00 65653210edf35c2472f5c4963b028f67c73e80ae Add headers for THM 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add headers for THM 15.0.0.

v2: squash in updates (Alex)

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add SMUIO 15.0.0 headers 2026-01-08T16:41:25+00:00 Alex Deucher alexander.deucher@amd.com 2025-12-05T15:57:29+00:00 29f560a5238d6b9170ef9b63b5718e760eec4b24 Add headers for SMUIO 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add headers for SMUIO 15.0.0.

v2: squash in updates (Alex)

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Port over some missing registers and bits from GC 10.1 to 10.3 (v2) 2026-01-05T22:00:01+00:00 Tom St Denis tom.stdenis@amd.com 2025-12-02T15:05:51+00:00 5e213a985d103ecd348ed4e9ae71292d86be9a71 v2: Added SPI bits to sh_mask header Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
v2: Added SPI bits to sh_mask header

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add UMA allocation setting helpers 2026-01-05T21:59:58+00:00 Yo-Jung Leo Lin (AMD) Leo.Lin@amd.com 2025-12-12T07:59:15+00:00 379a3160633a469da240f40948464f20582c11e9 On some platforms, UMA allocation size can be set using the ATCS methods. Add helper functions to interact with this functionality. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
On some platforms, UMA allocation size can be set using the ATCS
methods. Add helper functions to interact with this functionality.

Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: parse UMA size-getting/setting bits in ATCS mask 2026-01-05T21:59:58+00:00 Yo-Jung Leo Lin (AMD) Leo.Lin@amd.com 2025-12-12T07:59:13+00:00 6f3b631e395b971c7320830920185a7a2b44090f The capabilities of getting and setting VRAM carveout size are exposed in the ATCS mask. Parse and store these capabilities for future use. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
The capabilities of getting and setting VRAM carveout size are exposed
in the ATCS mask. Parse and store these capabilities for future use.

Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: RLC-G VF Register Access Interface 2026-01-05T21:59:57+00:00 Bokun Zhang bokun.zhang@amd.com 2025-10-27T13:45:33+00:00 0dd72af5528a404fca78ef0cad26582d34560c9b - Implement Gfx v12.1 VFi interface under SRIOV - Redirect all RLCG interface access to new function after Gfx v12.1 v2: squash in register updates Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
- Implement Gfx v12.1 VFi interface under SRIOV
- Redirect all RLCG interface access to new function after
  Gfx v12.1

v2: squash in register updates

Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>