linux-toradex.git/drivers/gpu/drm/msm/adreno, branch v4.11

drm/msm: Make sure to detach the MMU during GPU cleanup

2017-04-03T20:09:37+00:00

We should be detaching the MMU before destroying the address
space. To do this cleanly, the detach has to happen in
adreno_gpu_cleanup() because it needs access to structs
in adreno_gpu.c.  Plus it is better symmetry to have
the attach and detach at the same code level.

Signed-off-by: Jordan Crouse 
Signed-off-by: Rob Clark

drm/msm: Fix wrong pointer check in a5xx_destroy

2017-04-03T20:09:34+00:00

Instead of checking for a5xx_gpu->gpmu_iova during destroy we
accidently check a5xx_gpu->gpmu_bo.

Signed-off-by: Jordan Crouse 
Signed-off-by: Rob Clark

drm/msm: adreno: fix build error without debugfs

2017-04-03T20:09:34+00:00

The newly added a5xx support fails to build when debugfs is diabled:

drivers/gpu/drm/msm/adreno/a5xx_gpu.c:849:4: error: 'struct msm_gpu_funcs' has no member named 'show'
drivers/gpu/drm/msm/adreno/a5xx_gpu.c:849:11: error: 'a5xx_show' undeclared here (not in a function); did you mean 'a5xx_irq'?

This adds a missing #ifdef.

Fixes: b5f103ab98c7 ("drm/msm: gpu: Add A5XX target support")
Cc: stable@vger.kernel.org
Signed-off-by: Arnd Bergmann 
Signed-off-by: Rob Clark

drm/msm: let gpu wire up it's own fault handler

2017-02-06T16:28:42+00:00

Signed-off-by: Rob Clark

drm/msm: drop quirks binding

2017-02-06T16:28:42+00:00

This was never documented or used in upstream dtb.  It is used by
downstream bindings from android device kernels.  But the quirks are
a property of the gpu revision, and as such are redundant to be listed
separately in dt.  Instead, move the quirks to the device table.

Signed-off-by: Rob Clark 
Reviewed-by: Eric Anholt

drm/msm: drop qcom,chipid

2017-02-06T16:28:42+00:00

The original way we determined the gpu version was based on downstream
bindings from android kernel.  A cleaner way is to get the version from
the compatible string.

Note that no upstream dtb uses these bindings.  But the code still
supports falling back to the legacy bindings (with a warning), so that
we are still compatible with the gpu dt node from android device
kernels.

Signed-off-by: Rob Clark 
Reviewed-by: Eric Anholt 
Acked-by: Rob Herring

drm/msm: remove qcom,gpu-pwrlevels bindings

2017-02-06T16:28:42+00:00

The plan is to use the OPP bindings.  For now, remove the documentation
for qcom,gpu-pwrlevels, and make the driver fall back to a safe low
clock if the node is not present.

Note that no upstream dtb use this node.  For now we keep compatibility
with this node to avoid breaking compatibility with downstream android
dt files.

Signed-off-by: Rob Clark 
Reviewed-by: Eric Anholt 
Acked-by: Rob Herring

drm/msm: fix potential null ptr issue in non-iommu case

2017-01-13T15:23:00+00:00

Fixes: 9cb07b099fb ("drm/msm: support multiple address spaces")
Reported-by: Riku Voipio 
Signed-off-by: Rob Clark

drm/msm: Ensure that the hardware write pointer is valid

2016-12-29T20:02:58+00:00

Currently the value written to CP_RB_WPTR is calculated on the fly as
(rb->next - rb->start). But as the code is designed rb->next is wrapped
before writing the commands so if a series of commands happened to
fit perfectly in the ringbuffer, rb->next would end up being equal to
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.

The easiest way to fix this is to mask WPTR when writing it to the
hardware; it makes the hardware happy and the rest of the ringbuffer
math appears to work and there isn't any point in upsetting anything.

Signed-off-by: Jordan Crouse 
[squash in is_power_of_2() check]
Signed-off-by: Rob Clark

drm/msm: gpu: Add support for the GPMU

2016-11-28T20:14:16+00:00

Most 5XX targets have GPMU (Graphics Power Management Unit) that
handles a lot of the heavy lifting for power management including
thermal and limits management and dynamic power collapse. While
the GPMU itself is optional, it is usually nessesary to hit
aggressive power targets.

The GPMU firmware needs to be loaded into the GPMU at init time via a
shared hardware block of registers. Using the GPU to write the microcode
is more efficient than using the CPU so at first load create an indirect
buffer that can be executed during subsequent initalization sequences.

After loading the GPMU gets initalized through a shared register
interface and then we mostly get out of its way and let it do
its thing.

Signed-off-by: Jordan Crouse 
Signed-off-by: Rob Clark