linux-toradex.git/drivers/gpu/drm, branch v2.6.31.2

drm/i915: Handle ERESTARTSYS during page fault

2009-10-05T16:33:02+00:00

commit c715089f49844260f1eeae8e3b55af9468ba1325 upstream.

During a page fault and rebinding the buffer there exists a window for a
signal to arrive during the i915_wait_request() and trigger a
ERESTARTSYS. This used to be handled by returning SIGBUS and thereby
killing the application. Try 'cairo-perf-trace & cairo-test-suite' and
watch X go boom!

The solution as suggested by H. Peter Anvin is to simply return NOPAGE and
leave the higher layers to spot we did not fill the page and resubmit
the page fault.

Signed-off-by: Chris Wilson 
[anholt: Mostly squash it with another commit]
Signed-off-by: Greg Kroah-Hartman

agp/intel: Fix the pre-9xx chipset flush.

2009-10-05T16:32:12+00:00

commit e517a5e97080bbe52857bd0d7df9b66602d53c4d upstream.

Ever since we enabled GEM, the pre-9xx chipsets (particularly 865) have had
serious stability issues.  Back in May a wbinvd was added to the DRM to
work around much of the problem.  Some failure remained -- easily visible
by dragging a window around on an X -retro desktop, or by looking at bugzilla.

The chipset flush was on the right track -- hitting the right amount of
memory, and it appears to be the only way to flush on these chipsets, but the
flush page was mapped uncached.  As a result, the writes trying to clear the
writeback cache ended up bypassing the cache, and not flushing anything!  The
wbinvd would flush out other writeback data and often cause the data we wanted
to get flushed, but not always.  By removing the setting of the page to UC
and instead just clflushing the data we write to try to flush it, we get the
desired behavior with no wbinvd.

This exports clflush_cache_range(), which was laying around and happened to
basically match the code I was otherwise going to copy from the DRM.

Signed-off-by: Eric Anholt 
Signed-off-by: Brice Goglin 
Signed-off-by: Greg Kroah-Hartman

drm/i915: fix tiling on IGDNG

2009-10-05T16:32:11+00:00

commit 553bd149bb2de7848b2b84642876f27202421368 upstream.

It seems that on IGDNG the same swizzling setup always applys.
And front buffer tiling needs to set address swizzle in display
arb control too.

Fix plane tricle feed setting in v1 which should be disable bit,
and always setup address swizzle to let hardware care for buffer
tiling in all cases.

Signed-off-by: Zhenyu Wang 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/I915: Use the CRT DDC to get the EDID for DVI-connector on Mac

2009-10-05T16:32:11+00:00

commit 57cdaf90f5f607eb029356074fefb66c9b1c0659 upstream.

mac Mini's have a single DDC line on the DVI connector, shared between the
analog link and the digital link. So, if DDC isn't detected on GPIOE (the
usual SDVO DDC link), try GPIOA (the usual VGA DDC link) when there isn't a
VGA monitor connected.

Signed-off-by: Keith Packard 
Signed-off-by: Zhao Yakui 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Fix LVDS panel fitting on Arrandale

2009-10-05T16:32:10+00:00

commit 8dd81a381e8886129c0923f1fe22ff5ca36ae8da upstream.

Arrandale has new window based method for panel fitting.
This one enables full screen aspect scaling on LVDS. It fixes
standard mode display failure on LVDS for Arrandale.

Signed-off-by: Zhenyu Wang 
Signed-off-by: Jesse Barnes 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Remove DAC disable in CRT force detect on IGDNG

2009-10-05T16:32:09+00:00

commit 730915d65f9e763de9dc26c5f1b8abaae775b243 upstream.

This is not required on newer stepping hardware to get
reliable force detect status. Removing this fixes screen
blank flicker in CRT detect on IGDNG.

Signed-off-by: Zhenyu Wang 
Signed-off-by: Jesse Barnes 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Fix SSC frequence for IGDNG

2009-10-05T16:32:09+00:00

commit 339e5a4c78041cd7b473ddf0a81eb06a131127bb upstream.

IGDNG LVDS SSC uses 120Mhz freq. This fixes one
1600x900 LVDS panel black issue on IGDNG with SSC enabled.

Signed-off-by: Zhenyu Wang 
Signed-off-by: Jesse Barnes 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Fix typo for wrong LVDS clock setting on IGDNG

2009-10-05T16:32:08+00:00

commit b09aea7fb38f328c02e9f9b79617cabed02455e4 upstream.

New register for PCH LVDS on IGDNG should be used.
This is a copy-n-paste typo. This fixes possible dual
channel LVDS panel failure on IGDNG.

Signed-off-by: Zhenyu Wang 
Signed-off-by: Jesse Barnes 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Check that the relocation points to within the target

2009-10-05T16:32:07+00:00

commit cd0b9fb400ba775737bdc3874c4cbee4047e66d8 upstream.

Eric noted a potential concern with the low bits not being strictly used
as part of the absolute offset (instead part of the command stream to the
GPU), but in practice that should not be an issue.

Signed-off-by: Chris Wilson 
Tested-by: Andy Whitcroft 
Cc: Eric Anholt 
Signed-off-by: Jesse Barnes 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Add buffer to inactive list immediately during fault

2009-10-05T16:32:07+00:00

commit 4960aaca14010b9ff92e5726dd178cbd6805d412 upstream.

If we failed to set the domain, the buffer was no longer being tracked
on any list.

Signed-off-by: Chris Wilson 
Signed-off-by: Jesse Barnes 
Signed-off-by: Greg Kroah-Hartman