linux-toradex.git/drivers/gpu/drm, branch v2.6.33.5

drm/i915: Disable FBC on 915GM and 945GM.

2010-05-26T21:32:10+00:00

commit 8d06a1e1e9c69244f08beb7d17146483f9dcd120 upstream.

It is causing hangs after a suspend/resume cycle with the default
powersave=1 module option on these chipsets since 2.6.32-rc.

BugLink: http://bugs.launchpad.net/bugs/492392
Signed-off-by: Robert Hooker 
Acked-by: Jesse Barnes 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: fix non-Ironlake 965 class crashes

2010-05-26T21:32:06+00:00

commit 1918ad77f7f908ed67cf37c505c6ad4ac52f1ecf upstream.

My PIPE_CONTROL fix (just sent via Eric's tree) was buggy; I was
testing a whole set of patches together and missed a conversion to the
new HAS_PIPE_CONTROL macro, which will cause breakage on non-Ironlake
965 class chips.  Fortunately, the fix is trivial and has been tested.

Be sure to use the HAS_PIPE_CONTROL macro in i915_get_gem_seqno, or
we'll end up reading the wrong graphics memory, likely causing hangs,
crashes, or worse.

Reported-by: Zdenek Kabelac 
Reported-by: Toralf Förster 
Tested-by: Toralf Förster 
Signed-off-by: Jesse Barnes 
Signed-off-by: Linus Torvalds 
Signed-off-by: Greg Kroah-Hartman

drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge

2010-05-26T21:32:05+00:00

commit e552eb7038a36d9b18860f525aa02875e313fe16 upstream.

Since 965, the hardware has supported the PIPE_CONTROL command, which
provides fine grained GPU cache flushing control.  On recent chipsets,
this instruction is required for reliable interrupt and sequence number
reporting in the driver.

So add support for this instruction, including workarounds, on Ironlake
and Sandy Bridge hardware.

https://bugs.freedesktop.org/show_bug.cgi?id=27108

Signed-off-by: Jesse Barnes 
Tested-by: Chris Wilson 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: fix tiling limits for i915 class hw v2

2010-05-12T22:02:30+00:00

commit c36a2a6de59e4a141a68b7575de837d3b0bd96b3 upstream.

Current code is definitely crap: Largest pitch allowed spills into
the TILING_Y bit of the fence registers ... :(

I've rewritten the limits check under the assumption that 3rd gen hw
has a 3d pitch limit of 8kb (like 2nd gen). This is supported by an
otherwise totally misleading XXX comment.

This bug mostly resulted in tiling-corrupted pixmaps because the kernel
allowed too wide buffers to be tiled. Bug brought to the light by the
xf86-video-intel 2.11 release because that unconditionally enabled
tiling for pixmaps, relying on the kernel to check things. Tiling for
the framebuffer was not affected because the ddx does some additional
checks there ensure the buffer is within hw-limits.

v2: Instead of computing the value that would be written into the
hw fence registers and then checking the limits simply check whether
the stride is above the 8kb limit. To better document the hw, add
some WARN_ONs in i915_write_fence_reg like I've done for the i830
case (using the right limits).

Signed-off-by: Daniel Vetter 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27449
Tested-by: Alexander Lam 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.

2010-05-12T22:02:30+00:00

commit bad720ff3e8e47a04bd88d9bbc8317e7d7e049d3 upstream.

[needed for stable as it's just a bunch of macros that other drm patches
need, it changes no code functionality besides adding support for a new
device type. - gregkh]

Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/radeon/kms: fix rs600 tlb flush

2010-04-26T14:47:55+00:00

commit 30f69f3fb20bd719b5e1bf879339914063d38f47 upstream.

Typo in in flush leaded to no flush of the RS600 tlb which
ultimately leaded to massive system ram corruption, with
this patch everythings seems to work properly.

Signed-off-by: Jerome Glisse 
Signed-off-by: Dave Airlie 
Signed-off-by: Greg Kroah-Hartman

drm/radeon/kms: fix tv dac conflict resolver

2010-04-26T14:47:55+00:00

commit 08d075116db3592db218bfe0f554cd93c9e12505 upstream.

On systems with the tv dac shared between DVI and TV,
we can only use the dac for one of the connectors.
However, when using a digital monitor on the DVI port,
you can use the dac for the TV connector just fine.
Check the use_digital status when resolving the conflict.

Fixes fdo bug 27649, possibly others.

Signed-off-by: Alex Deucher 
Signed-off-by: Dave Airlie 
Signed-off-by: Greg Kroah-Hartman

drm/radeon/kms: disable the tv encoder when tv/cv is not in use

2010-04-26T14:47:55+00:00

commit d3a67a43b0460bae3e2ac14092497833344ac10d upstream.

Switching between TV and VGA caused VGA to break on some systems
since the TV encoder was left enabled when VGA was used.

fixes fdo bug 25520.

Signed-off-by: Alex Deucher 
Signed-off-by: Dave Airlie 
Signed-off-by: Greg Kroah-Hartman

drm/radeon/kms: more atom parser fixes (v2)

2010-04-26T14:47:55+00:00

commit 65384a1d41c4e91f0b49d90d11b7f424d6e5c58e upstream.

shr/shl ops need the full dst rather than the pre-masked
version.  Fixes fdo bug 27478 and kernel bug 15738.

v2: remove some unsed vars, add comments

Signed-off-by: Alex Deucher 
Signed-off-by: Dave Airlie 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Add no_lvds entry for the Clientron U800

2010-04-26T14:47:55+00:00

commit 9875557ee8247c3f7390d378c027b45c7535a224 upstream.

BugLink: http://bugs.launchpad.net/ubuntu/bugs/544671

This system claims to have a LVDS but has not.

Signed-off-by: Stephane Graber 
Signed-off-by: Stefan Bader 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman