linux-toradex.git/drivers/gpu, branch v2.6.32.7

drm/i915: try another possible DDC bus for the SDVO device with multiple outputs

2010-01-25T18:49:39+00:00

commit 7c3f0a2726fed78e0e0afe3b6fc3c1f5b298e447 upstream.

There exist multiple DDC buses for the SDVO cards with multiple outputs.
When we can't get the EDID by using the select DDC bus, we can try the other
possible DDC bus to see whether the EDID can be obtained.

https://bugs.freedesktop.org/show_bug.cgi?id=23842

Signed-off-by: Zhao Yakui 
Tested-by: Sebastien Caty 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Read the response after issuing DDC bus switch command

2010-01-25T18:49:38+00:00

commit 6a304caf0bf9c429fc261f260b86cabf5bde2cbb upstream.

For some SDVO cards based on conexant chip, we can't read the EDID if
we don't read the response after issuing SDVO DDC bus switch
command.

From the SDVO spec once when another I2C transaction is finished after
completing the I2C transaction of issuing the bus switch command, it
will be switched back to the SDVO internal state again. So we can't
initiate a new I2C transaction to read the response after issuing the
DDC bus switch command. Instead we should issue DDC bus switch command
and read the response in the same I2C transaction.

https://bugs.freedesktop.org/show_bug.cgi?id=23842
https://bugs.freedesktop.org/show_bug.cgi?id=24458
https://bugs.freedesktop.org/show_bug.cgi?id=24522
https://bugs.freedesktop.org/show_bug.cgi?id=24282

Signed-off-by: Zhao Yakui 
Tested-by: Sebastien Caty 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: remove loop in Ironlake interrupt handler

2010-01-22T23:18:03+00:00

commit c7c85101afd0cb8ce497456d12ee1cad4aad152f upstream.

On Ironlake, there is an interrupt master control bit. With the bit
disabled before clearing IIR, we do not need to handle extra interrupt
in a loop. This patch removes the loop in Ironlake interrupt handler.
It fixed irq lost issue on some Ironlake platforms.

Signed-off-by: Zou Nan hai 
Signed-off-by: Zhenyu Wang 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: remove render reclock support

2010-01-18T18:19:48+00:00

commit cda9d05c499093c67b4a376a15009923acc2127a upstream.

This code generally fails to adjust the render clock, and when it does,
it conflicts with some other register settings and can cause problems.

So remove this code altogether.  I'm reworking it now to do the right
thing, but the only bit it will share is the VBT check for whether
reclocking is supported, so I'm leaving that bit.

Reverts most of 652c393a3368af84359da37c45afc35a91144960 ("add dynamic
clock frequency control"), though for many the regressions showed up
in the later 181a5336d6cc836f05507410d66988c483ad0154 ("Fix render
reclock availability detection").

Signed-off-by: Jesse Barnes 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: fix unused var

2010-01-18T18:19:28+00:00

commit 29bd0ae25f8cb96b63560c2cbccec77b425e1603 upstream.

drivers/gpu/drm/i915/i915_dma.c: In function 'i915_driver_load':
drivers/gpu/drm/i915/i915_dma.c:1114: warning: 'll_base' may be used uninitialized in this function

Partly this is because gcc isn't smart enough.  But `ll_base' does get used
uninitialised in the DRM_DEBUG() call.

Cc: Jesse Barnes 
Cc: Eric Anholt 
Cc: Dave Airlie 
Signed-off-by: Andrew Morton 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Select the correct BPC for LVDS on Ironlake

2010-01-18T18:19:27+00:00

commit e5a95eb778690bc864eb330202d2c1b974caaeb4 upstream.

Select the correct BPC for LVDS on Ironlake. If it is 18-bit LVDS panel,
the BPC will be 6. When it is 24-bit LVDS panel, the BPC will 8.
At the same time the BPC will be 8 when the output device is CRT/HDMI/DP.

Signed-off-by: Zhao Yakui 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on Ironlake

2010-01-18T18:19:25+00:00

commit 8faf3b317471179c02db339aa80955a2e88c036d upstream.

Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on Ironlake.

Signed-off-by: Zhao Yakui 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Enable/disable the dithering for LVDS based on VBT setting

2010-01-18T18:19:24+00:00

commit 898822ce9561ab9b58a7eb60580a162a83dadecd upstream.

Enable/disable the dithering for LVDS based on VBT setting. On the 965/g4x
platform the dithering flag is defined in LVDS register. And on the ironlake
the dithering flag is defined in pipeconf register.

Signed-off-by: Zhao Yakui 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

drm: remove address mask param for drm_pci_alloc()

2010-01-18T18:19:23+00:00

commit e6be8d9d17bd44061116f601fe2609b3ace7aa69 upstream.

drm_pci_alloc() has input of address mask for setting pci dma
mask on the device, which should be properly setup by drm driver.
And leave it as a param for drm_pci_alloc() would cause confusion
or mistake would corrupt the correct dma mask setting, as seen on
intel hw which set wrong dma mask for hw status page. So remove
it from drm_pci_alloc() function.

Signed-off-by: Zhenyu Wang 
Signed-off-by: Dave Airlie 
Signed-off-by: Greg Kroah-Hartman

drm/i915: Permit pinning whilst the device is 'suspended'

2010-01-18T18:19:23+00:00

commit e3d8affb0d2d95f2da61e30ce86b33177feb91e8 upstream.

As pinning (allocating and binding GTT memory) does not actually invoke
GPU commands, it is safe, and indeed is attempted, during resumption
from suspension:

  [drm:intel_init_clock_gating] *ERROR* failed to pin power context: -16

Signed-off-by: Chris Wilson 
Reported-by: Hugh Dickins 
Signed-off-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman