<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/hwmon/coretemp.c, branch v2.6.32.33</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>hwmon: (coretemp) Skip duplicate CPU entries</title>
<updated>2010-08-02T17:20:43+00:00</updated>
<author>
<name>Jean Delvare</name>
<email>khali@linux-fr.org</email>
</author>
<published>2010-07-09T14:22:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=696f12076eb2d2217e67dcae62c8a436b4ec524b'/>
<id>696f12076eb2d2217e67dcae62c8a436b4ec524b</id>
<content type='text'>
commit d883b9f0977269d519469da72faec6a7f72cb489 upstream.

On hyper-threaded CPUs, each core appears twice in the CPU list. Skip
the second entry to avoid duplicate sensors.

Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Acked-by: Huaxu Wan &lt;huaxu.wan@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit d883b9f0977269d519469da72faec6a7f72cb489 upstream.

On hyper-threaded CPUs, each core appears twice in the CPU list. Skip
the second entry to avoid duplicate sensors.

Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Acked-by: Huaxu Wan &lt;huaxu.wan@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>hwmon: (coretemp) Properly label the sensors</title>
<updated>2010-08-02T17:20:43+00:00</updated>
<author>
<name>Jean Delvare</name>
<email>khali@linux-fr.org</email>
</author>
<published>2010-07-09T14:22:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a4a3b1fb8a7e81648884840c3aabe38458202618'/>
<id>a4a3b1fb8a7e81648884840c3aabe38458202618</id>
<content type='text'>
commit 3f4f09b4be35d38d6e2bf22c989443e65e70fc4c upstream.

Don't assume that CPU entry number and core ID always match. It
worked in the simple cases (single CPU, no HT) but fails on
multi-CPU systems.

Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Acked-by: Huaxu Wan &lt;huaxu.wan@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 3f4f09b4be35d38d6e2bf22c989443e65e70fc4c upstream.

Don't assume that CPU entry number and core ID always match. It
worked in the simple cases (single CPU, no HT) but fails on
multi-CPU systems.

Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Acked-by: Huaxu Wan &lt;huaxu.wan@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>hwmon: (coretemp) Add missing newline to dev_warn() message</title>
<updated>2010-04-01T22:58:48+00:00</updated>
<author>
<name>Dean Nelson</name>
<email>dnelson@redhat.com</email>
</author>
<published>2010-03-29T20:03:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=66730dc9cceb31f8425aa52d8c5ee99c348a07b9'/>
<id>66730dc9cceb31f8425aa52d8c5ee99c348a07b9</id>
<content type='text'>
commit 4d7a5644e4adfafe76c2bd8ee168e3f3b5dae3a8 upstream.

Add missing newline to dev_warn() message string. This is more of an issue
with older kernels that don't automatically add a newline if it was missing
from the end of the previous line.

Signed-off-by: Dean Nelson &lt;dnelson@redhat.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 4d7a5644e4adfafe76c2bd8ee168e3f3b5dae3a8 upstream.

Add missing newline to dev_warn() message string. This is more of an issue
with older kernels that don't automatically add a newline if it was missing
from the end of the previous line.

Signed-off-by: Dean Nelson &lt;dnelson@redhat.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs</title>
<updated>2010-01-18T18:19:42+00:00</updated>
<author>
<name>Yong Wang</name>
<email>yong.y.wang@linux.intel.com</email>
</author>
<published>2010-01-10T19:52:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4052fbfb24712ee7bb31c4c813d551712d7a4e4e'/>
<id>4052fbfb24712ee7bb31c4c813d551712d7a4e4e</id>
<content type='text'>
commit 1fe63ab47a617ee95f562eaa7ddbbc59981ff8c6 upstream.

The max junction temperature of Atom N450/D410/D510 CPUs is 100 degrees
Celsius. Since these CPUs are always coupled with Intel NM10 chipset in
one package, the best way to verify whether an Atom CPU is N450/D410/D510
is to check the host bridge device.

Signed-off-by: Yong Wang &lt;yong.y.wang@intel.com&gt;
Acked-by: Huaxu Wan &lt;huaxu.wan@intel.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 1fe63ab47a617ee95f562eaa7ddbbc59981ff8c6 upstream.

The max junction temperature of Atom N450/D410/D510 CPUs is 100 degrees
Celsius. Since these CPUs are always coupled with Intel NM10 chipset in
one package, the best way to verify whether an Atom CPU is N450/D410/D510
is to check the host bridge device.

Signed-off-by: Yong Wang &lt;yong.y.wang@intel.com&gt;
Acked-by: Huaxu Wan &lt;huaxu.wan@intel.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>hwmon: (coretemp) Add Lynnfield CPU</title>
<updated>2009-09-23T20:59:43+00:00</updated>
<author>
<name>Huaxu Wan</name>
<email>huaxu.wan@linux.intel.com</email>
</author>
<published>2009-09-23T20:59:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=fa08acd7d16cd7ea8114f3844b0ef2505a4276a8'/>
<id>fa08acd7d16cd7ea8114f3844b0ef2505a4276a8</id>
<content type='text'>
Add Lynnfield processor support. Lynnfield is a quad-core Nehalem
based microprocessor for Desktop market, which is introduced in
September 2009.

Signed-off-by: Huaxu Wan &lt;huaxu.wan@linux.intel.com&gt;
Signed-off-by: Kent Liu &lt;kent.liu@linux.intel.com&gt;
Acked-by: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Lynnfield processor support. Lynnfield is a quad-core Nehalem
based microprocessor for Desktop market, which is introduced in
September 2009.

Signed-off-by: Huaxu Wan &lt;huaxu.wan@linux.intel.com&gt;
Signed-off-by: Kent Liu &lt;kent.liu@linux.intel.com&gt;
Acked-by: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>hwmon: (coretemp) Add support for Penryn mobile CPUs</title>
<updated>2009-09-23T20:59:42+00:00</updated>
<author>
<name>Rudolf Marek</name>
<email>r.marek@assembler.cz</email>
</author>
<published>2009-09-23T20:59:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=eccfed42215bebda0acc3158c1a4ff8325dea275'/>
<id>eccfed42215bebda0acc3158c1a4ff8325dea275</id>
<content type='text'>
Following patch adds support for mobile Penryn CPUs. Intel documents this
poorly. I asked the Coretemp author for some help. This is totally untested and
may not work. Please test!

Signed-off-by: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Cc: Huaxu Wan &lt;huaxu.wan@linux.intel.com&gt;
Cc: Kent Liu &lt;kent.liu@linux.intel.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Following patch adds support for mobile Penryn CPUs. Intel documents this
poorly. I asked the Coretemp author for some help. This is totally untested and
may not work. Please test!

Signed-off-by: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Cc: Huaxu Wan &lt;huaxu.wan@linux.intel.com&gt;
Cc: Kent Liu &lt;kent.liu@linux.intel.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>hwmon: (coretemp) Fix Atom CPUs support</title>
<updated>2009-09-23T20:59:42+00:00</updated>
<author>
<name>Rudolf Marek</name>
<email>r.marek@assembler.cz</email>
</author>
<published>2009-09-23T20:59:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=708a62bcd5f699756bae81491e64648fbf19e2a4'/>
<id>708a62bcd5f699756bae81491e64648fbf19e2a4</id>
<content type='text'>
Fix Atom CPUs support. Intel documents TjMax at 90 degrees C but
some Atoms may have 125 degrees C (this is undocumented speculation).

Signed-off-by: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Cc: Huaxu Wan &lt;huaxu.wan@linux.intel.com&gt;
Cc: Kent Liu &lt;kent.liu@linux.intel.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix Atom CPUs support. Intel documents TjMax at 90 degrees C but
some Atoms may have 125 degrees C (this is undocumented speculation).

Signed-off-by: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Cc: Huaxu Wan &lt;huaxu.wan@linux.intel.com&gt;
Cc: Kent Liu &lt;kent.liu@linux.intel.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/hwmon/coretemp.c: enable the Intel Atom</title>
<updated>2009-09-22T14:17:48+00:00</updated>
<author>
<name>Michael Riepe</name>
<email>michael.riepe@googlemail.com</email>
</author>
<published>2009-09-22T00:04:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0bf41d9f414a5cf558aff234a0ff486257537574'/>
<id>0bf41d9f414a5cf558aff234a0ff486257537574</id>
<content type='text'>
Enable the coretemp driver on an Intel Atom.

I'm not sure if the readings are correct, however - on my 330, the driver
reports values between 27 and 41 °C (with core1 being about 8°C hotter
than core0, given the same load).  Maybe the maximum temperature of 100 °C
is wrong for Atom CPUs.

Cc: Arjan van de Ven &lt;arjan@infradead.org&gt;
Cc: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable the coretemp driver on an Intel Atom.

I'm not sure if the readings are correct, however - on my 330, the driver
reports values between 27 and 41 °C (with core1 being about 8°C hotter
than core0, given the same load).  Maybe the maximum temperature of 100 °C
is wrong for Atom CPUs.

Cc: Arjan van de Ven &lt;arjan@infradead.org&gt;
Cc: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>coretemp: recognize Nehalem CPUs</title>
<updated>2008-08-15T15:35:44+00:00</updated>
<author>
<name>Darrick J. Wong</name>
<email>djwong@us.ibm.com</email>
</author>
<published>2008-08-15T07:40:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=34c86c1e622ec77ba81c01969003bbc8e15156f3'/>
<id>34c86c1e622ec77ba81c01969003bbc8e15156f3</id>
<content type='text'>
Add in the CPUID for Nehalem chips.

Signed-off-by: Darrick J. Wong &lt;djwong@us.ibm.com&gt;
Cc: Kent Liu &lt;kent.liu@linux.intel.com&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add in the CPUID for Nehalem chips.

Signed-off-by: Darrick J. Wong &lt;djwong@us.ibm.com&gt;
Cc: Kent Liu &lt;kent.liu@linux.intel.com&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>hwmon: (coretemp) Add Penryn CPU to coretemp</title>
<updated>2008-02-18T03:08:37+00:00</updated>
<author>
<name>Rudolf Marek</name>
<email>r.marek@assembler.cz</email>
</author>
<published>2008-01-17T23:50:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=ae770152c801f10a91e5e86597a39b5f9ccf2d0d'/>
<id>ae770152c801f10a91e5e86597a39b5f9ccf2d0d</id>
<content type='text'>
This patch adds support for family 0x17, which has Penryn Core. It should also
cover the 8 cores Xeons.

Can someone test please? I think it should work.

Signed-off-by: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Acked-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Signed-off-by: Mark M. Hoffman &lt;mhoffman@lightlink.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds support for family 0x17, which has Penryn Core. It should also
cover the 8 cores Xeons.

Can someone test please? I think it should work.

Signed-off-by: Rudolf Marek &lt;r.marek@assembler.cz&gt;
Acked-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Signed-off-by: Mark M. Hoffman &lt;mhoffman@lightlink.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
