linux-toradex.git/drivers/hwtracing, branch v5.17-rc4

coresight: core: Fix typo in a comment

2021-12-13T18:54:07+00:00

The double `the' in the comment in line 732 is repeated. Remove one
of them from the comment.

Signed-off-by: Jason Wang 
Link: https://lore.kernel.org/r/20211211090221.241529-1-wangborong@cdjrlc.com
[Fixed capital letter in title]
Signed-off-by: Mathieu Poirier

coresight: configfs: Allow configfs to activate configuration

2021-11-26T18:34:27+00:00

Adds configfs attributes to allow a configuration to be enabled for use
when sysfs is used to control CoreSight.

perf retains independent enabling of configurations.

Signed-off-by: Mike Leach 
Link: https://lore.kernel.org/r/20211124200038.28662-6-mike.leach@linaro.org
Signed-off-by: Mathieu Poirier

coresight: syscfg: Update load API for config loadable modules

2021-11-26T18:28:09+00:00

CoreSight configurations and features can be added as kernel loadable
modules. This patch updates the load owner API to ensure that the module
cannot be unloaded either:
1) if the config it supplies is in use
2) if the module is not the last in the load order list.

Signed-off-by: Mike Leach 
Link: https://lore.kernel.org/r/20211124200038.28662-4-mike.leach@linaro.org
Signed-off-by: Mathieu Poirier

coresight: configuration: Update API to permit dynamic load/unload

2021-11-26T18:27:35+00:00

Expand the configuration API to allow dynamic runtime load and unload of
configurations and features.

On load, configurations and features are tagged with a "load owner" that
is used to determine sets that were loaded together in a given API call.

To unload the API uses the load owner to unload all elements previously
loaded by that owner.

The API also records the order in which different owners loaded
their elements into the system. Later loading configurations can use
previously loaded features, creating load dependencies. Therefore unload
is enforced strictly in the reverse order to load.

A load owner will be an additional loadable module, or a configuration
loaded via configfs.

Signed-off-by: Mike Leach 
Link: https://lore.kernel.org/r/20211124200038.28662-3-mike.leach@linaro.org
Signed-off-by: Mathieu Poirier

coresight: configuration: Update API to introduce load owner concept

2021-11-26T18:27:21+00:00

Update the existing load API to introduce a "load owner" concept.

This allows the tracking of the loaded configurations and features against
the loading owner type, to allow later unload according to owner.

A list of loaded configurations by owner is created.

The load owner infrastructure will be used in following patches
to implement dynanic load and unload, alongside dependency tracking.

Signed-off-by: Mike Leach 
Link: https://lore.kernel.org/r/20211124200038.28662-2-mike.leach@linaro.org
Signed-off-by: Mathieu Poirier

coresight: Use devm_bitmap_zalloc when applicable

2021-11-16T17:13:21+00:00

'drvdata->chs.guaranteed' is a bitmap. So use 'devm_bitmap_kzalloc()' to
simplify code, improve the semantic and avoid some open-coded arithmetic
in allocator arguments.

Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/a4b8454f560b70cedf0e4d06275787f08d576ee5.1635964610.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Mathieu Poirier

coresight: trbe: Work around write to out of range

2021-10-27T17:46:01+00:00

TRBE implementations affected by Arm erratum (2253138 or 2224489), could
write to the next address after the TRBLIMITR.LIMIT, instead of wrapping
to the TRBBASER. This implies that the TRBE could potentially corrupt :

  - A page used by the rest of the kernel/user (if the LIMIT = end of
    perf ring buffer)
  - A page within the ring buffer, but outside the driver's range.
    [head, head + size]. This may contain some trace data, may be
    consumed by the userspace.

We workaround this erratum by :
  - Making sure that there is at least an extra PAGE space left in the
    TRBE's range than we normally assign. This will be additional to other
    restrictions (e.g, the TRBE alignment for working around
    TRBE_WORKAROUND_OVERWRITE_IN_FILL_MODE, where there is a minimum of
    PAGE_SIZE. Thus we would have 2 * PAGE_SIZE)

  - Adjust the LIMIT to leave the last PAGE_SIZE out of the TRBE's allowed
    range (i.e, TRBEBASER...TRBLIMITR.LIMIT), by :

        TRBLIMITR.LIMIT -= PAGE_SIZE

Cc: Anshuman Khandual 
Cc: Mathieu Poirier 
Cc: Mike Leach 
Cc: Leo Yan 
Reviewed-by: Anshuman Khandual 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20211019163153.3692640-14-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier

coresight: trbe: Make sure we have enough space

2021-10-27T17:45:59+00:00

The TRBE driver makes sure that there is enough space for a meaningful
run, otherwise pads the given space and restarts the offset calculation
once. But there is no guarantee that we may find space or hit "no space".
Make sure that we repeat the step until, either :
  - We have the minimum space
   OR
  - There is NO space at all.

Cc: Anshuman Khandual 
Cc: Mathieu Poirier 
Cc: Mike Leach 
Cc: Leo Yan 
Reviewed-by: Anshuman Khandual 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20211019163153.3692640-13-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier

coresight: trbe: Add a helper to determine the minimum buffer size

2021-10-27T17:45:57+00:00

For the TRBE to operate, we need a minimum space available to collect
meaningful trace session. This is currently a few bytes, but we may need
to extend this for working around errata. So, abstract this into a helper
function.

Cc: Anshuman Khandual 
Cc: Mike Leach 
Cc: Mathieu Poirier 
Cc: Leo Yan 
Reviewed-by: Anshuman Khandual 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20211019163153.3692640-12-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier

coresight: trbe: Workaround TRBE errata overwrite in FILL mode

2021-10-27T17:45:56+00:00

ARM Neoverse-N2 (#2139208) and Cortex-A710(##2119858) suffers from
an erratum, which when triggered, might cause the TRBE to overwrite
the trace data already collected in FILL mode, in the event of a WRAP.
i.e, the TRBE doesn't stop writing the data, instead wraps to the base
and could write upto 3 cache line size worth trace. Thus, this could
corrupt the trace at the "BASE" pointer.

The workaround is to program the write pointer 256bytes from the
base, such that if the erratum is triggered, it doesn't overwrite
the trace data that was captured. This skipped region could be
padded with ignore packets at the end of the session, so that
the decoder sees a continuous buffer with some padding at the
beginning. The trace data written at the base is considered
lost as the limit could have been in the middle of the perf
ring buffer, and jumping to the "base" is not acceptable.
We set the flags already to indicate that some amount of trace
was lost during the FILL event IRQ. So this is fine.

One important change with the work around is, we program the
TRBBASER_EL1 to current page where we are allowed to write.
Otherwise, it could overwrite a region that may be consumed
by the perf. Towards this, we always make sure that the
"handle->head" and thus the trbe_write is PAGE_SIZE aligned,
so that we can set the BASE to the PAGE base and move the
TRBPTR to the 256bytes offset.

Cc: Mike Leach 
Cc: Mathieu Poirier 
Cc: Anshuman Khandual 
Cc: Leo Yan 
Reviewed-by: Anshuman Khandual 
Signed-off-by: Suzuki K Poulose 
Link: https://lore.kernel.org/r/20211019163153.3692640-11-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier