linux-toradex.git/drivers/iio/adc/Makefile, branch master

iio: adc: ltc2378: Add support for LTC2378-20 and similar ADCs

2026-08-03T21:32:33+00:00

Support for LTC2378-20 and similar analog-to-digital converters.

Reviewed-by: Andy Shevchenko 
Reviewed-by: David Lechner 
Signed-off-by: Marcelo Schmitt 
Signed-off-by: Jonathan Cameron

iio: adc: add ti-ads112c14 driver

2026-07-19T23:42:25+00:00

Add a new driver for the TI ADS112C14/ADS122C14 ADC chips.

This first step is adding a very basic driver that only supports power
on/reset and reading the system monitor channels.

ADS112C14_SYS_MON_CHANNEL_SHORT is the last channel rather than being in
logical order by address to keep the voltage channels together and in
case we find we need to add variants of this channel with different
voltage reference later.

Signed-off-by: David Lechner (TI) 
Signed-off-by: Jonathan Cameron

iio: adc: versal-sysmon: add I2C driver

2026-07-02T15:43:51+00:00

Add an I2C transport driver for the Versal SysMon block. The SysMon
provides an I2C slave interface that allows an external master to
read voltage and temperature measurements through the same register
map used by the MMIO path.

The I2C command frame is an 8-byte structure containing a 4-byte data
payload, a 2-byte register offset, and a 1-byte instruction field.
Read operations send the frame with a read instruction, then receive
a 4-byte response containing the register value.

Events are not supported on the I2C path because there is no
interrupt line and the I2C regmap backend cannot be called from
atomic context.

Co-developed-by: Conall O'Griofa 
Signed-off-by: Conall O'Griofa 
Signed-off-by: Salih Erim 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Jonathan Cameron

iio: adc: add Versal SysMon driver

2026-07-02T15:43:51+00:00

Add the core driver and MMIO platform driver for the AMD/Xilinx Versal
System Monitor (SysMon) block.

The SysMon block resides in the platform management controller (PMC) and
provides on-chip voltage and temperature monitoring through a 10-bit,
200 kSPS ADC. It can monitor up to 160 voltage channels and 64
temperature satellites distributed across the SoC, with a consistent
sample rate of 8 kSPS per channel regardless of how many channels are
enabled.

The hardware also provides four aggregate temperature registers that
are always present regardless of the device tree configuration: the
current max and min across all active satellites, and the peak and
trough values recorded since the last hardware reset.

The driver is split into two compilation units:
  - versal-sysmon-core: Channel parsing, IIO registration, read_raw
  - versal-sysmon: MMIO platform driver with custom regmap accessors

Voltage results are stored in a 19-bit modified floating-point format
and converted to millivolts. Temperature results are stored in Q8.7
signed fixed-point Celsius format and converted to millicelsius.

The MMIO regmap backend uses a custom reg_write accessor that
automatically unlocks the NPI (NoC programming interface) lock
register before each write, as required by the hardware. The regmap
is configured with fast_io since the underlying MMIO accessors are
safe to call from atomic context.

Co-developed-by: Michal Simek 
Signed-off-by: Michal Simek 
Signed-off-by: Salih Erim 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Jonathan Cameron

iio: adc: mt6323-auxadc: add mt6323 PMIC AUXADC driver

2026-07-02T15:43:50+00:00

The mt6323 AUXADC is a 15-bit ADC used for system monitoring. This driver
provides support for reading various channels including battery and
charger voltages, battery and chip temperature, current sensing and
accessory detection.

Add a driver for the AUXADC found in the MediaTek mt6323 PMIC.

Tested-by: Ben Grisdale  # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar 
Reviewed-by: Andy Shevchenko 
Reviewed-by: David Lechner 
Signed-off-by: Jonathan Cameron

iio: adc: ad4691: add initial driver for AD4691 family

2026-05-31T10:04:36+00:00

Add support for the Analog Devices AD4691 family of high-speed,
low-power multichannel SAR ADCs: AD4691 (16-ch, 500 kSPS),
AD4692 (16-ch, 1 MSPS), AD4693 (8-ch, 500 kSPS) and
AD4694 (8-ch, 1 MSPS).

The driver implements a custom regmap layer over raw SPI to handle the
device's mixed 1/2/3/4-byte register widths and uses the standard IIO
read_raw/write_raw interface for single-channel reads.

The chip idles in Autonomous Mode so that single-shot read_raw can use
the internal oscillator without disturbing the hardware configuration.

Three voltage supply domains are managed: avdd (required), vio, and a
reference supply on either the REF pin (ref-supply, external buffer)
or the REFIN pin (refin-supply, uses the on-chip reference buffer;
REFBUF_EN is set accordingly). Hardware reset is performed by asserting
then deasserting the reset-gpios GPIO line (tRESETL minimum pulse width
is 10 ns, satisfied by function-call overhead); the driver then waits
300 µs for the chip to complete its internal reset sequence. A software
reset via SPI_CONFIG_A is used as fallback when no reset GPIO is
provided.

Accumulator channel masking for single-shot reads uses ACC_MASK_REG via
an ADDR_DESCENDING SPI write, which covers both mask bytes in a single
16-bit transfer.

Reviewed-by: David Lechner 
Signed-off-by: Radu Sabau 
Signed-off-by: Jonathan Cameron

iio: adc: Add support for QCOM PMIC5 Gen3 ADC

2026-02-23T20:23:32+00:00

The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
with all SW communication to ADC going through PMK8550 which
communicates with other PMICs through PBS.

One major difference is that the register interface used here is that
of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550.
There may be more than one SDAM used for ADC5 Gen3 and each has eight
channels, which may be used for either immediate reads (same functionality
as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements
(same as ADC_TM functionality).

By convention, we reserve the first channel of the first SDAM for all
immediate reads and use the remaining channels across all SDAMs for
ADC_TM monitoring functionality.

Add support for PMIC5 Gen3 ADC driver for immediate read functionality.
ADC_TM is implemented as an auxiliary thermal driver under this ADC
driver.

Signed-off-by: Jishnu Prakash 
Signed-off-by: Jonathan Cameron

iio: adc: Initial support for AD4134

2026-01-11T13:30:29+00:00

AD4134 is a 24-bit, 4-channel, simultaneous sampling, precision
analog-to-digital converter (ADC). The device can be managed through SPI or
direct control of pin logical levels (pin control mode). The AD4134 design
also features a dedicated bus for ADC sample data output. Though, this
initial driver for AD4134 only supports usual SPI connections.

Add basic support for AD4134 that enables single-shot ADC sample read.

Signed-off-by: Marcelo Schmitt 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Jonathan Cameron

iio: adc: Add support for ad4062

2025-12-31T17:59:25+00:00

The AD4060/AD4062 are versatile, 16-bit/12-bit, successive approximation
register (SAR) analog-to-digital converter (ADC) with low-power and
threshold monitoring modes.

Signed-off-by: Jorge Marques 
Signed-off-by: Jonathan Cameron

iio: adc: Add ti-ads1018 driver

2025-12-21T18:48:50+00:00

Add ti-ads1018 driver for Texas Instruments ADS1018 and ADS1118 SPI
analog-to-digital converters.

This chips' MOSI pin is shared with a data-ready interrupt. Defining
this interrupt in devicetree is optional, therefore we only create an
IIO trigger if one is found.

Handling this interrupt requires some considerations. When enabling the
trigger the CS line is tied low (active), thus we need to hold
spi_bus_lock() too, to avoid state corruption. This is done inside the
set_trigger_state() callback, to let users use other triggers without
wasting a bus lock.

Reviewed-by: Andy Shevchenko 
Signed-off-by: Kurt Borja 
Reviewed-by: David Lechner 
Signed-off-by: Jonathan Cameron