linux-toradex.git/drivers/irqchip/Makefile, branch v3.17-rc5 Linux kernel for Apalis and Colibri modules Merge branch 'irqchip/atmel-aic' into irqchip/core 2014-07-18T20:58:34+00:00 Jason Cooper jason@lakedaemon.net 2014-07-18T20:58:34+00:00 f0cf9d2facbe3aa93b302058c013729cbc1bca22 Topic branch set up to facilitate merging the rest of the series which removes the driver from arch code. 
Topic branch set up to facilitate merging the rest of the series which
removes the driver from arch code.
Merge tag 'tags/deps-irqchip-gic-3.17' into irqchip/core 2014-07-18T20:56:39+00:00 Jason Cooper jason@lakedaemon.net 2014-07-18T20:56:39+00:00 20c0c607605244dd237707bb07e7f2ffd82e8aa5 From local branch irqchip/gic, this is topic branch that was set up to facilitate merging other changes depending on the new GICv3 driver. 
From local branch irqchip/gic, this is topic branch that was set up to
facilitate merging other changes depending on the new GICv3 driver.
irqchip: atmel-aic: Add atmel AIC/AIC5 drivers 2014-07-17T13:30:35+00:00 Boris BREZILLON boris.brezillon@free-electrons.com 2014-07-10T17:14:18+00:00 b1479ebb772003461f0458a0b3a68cb1c4036288 Add AIC (Advanced Interrupt Controller) and AIC5 (AIC5 is an evolution of the AIC block) drivers. Put common code in irq-atmel-aic-common.c/.h so that both driver can access shared functions (this will ease maintenance). These drivers are only compatible with dt enabled board and replace the old implementation found in arch/arm/mach-at91/irq.c. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Link: https://lkml.kernel.org/r/1405012462-766-4-git-send-email-boris.brezillon@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net> 
Add AIC (Advanced Interrupt Controller) and AIC5 (AIC5 is an evolution of
the AIC block) drivers.
Put common code in irq-atmel-aic-common.c/.h so that both driver can access
shared functions (this will ease maintenance).

These drivers are only compatible with dt enabled board and replace the
old implementation found in arch/arm/mach-at91/irq.c.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Link: https://lkml.kernel.org/r/1405012462-766-4-git-send-email-boris.brezillon@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
irqchip: gic-v3: Initial support for GICv3 2014-07-08T22:11:47+00:00 Marc Zyngier marc.zyngier@arm.com 2014-06-30T15:01:31+00:00 021f653791ad17e03f98aaa7fb933816ae16f161 The Generic Interrupt Controller (version 3) offers services that are similar to GICv2, with a number of additional features: - Affinity routing based on the CPU MPIDR (ARE) - System register for the CPU interfaces (SRE) - Support for more that 8 CPUs - Locality-specific Peripheral Interrupts (LPIs) - Interrupt Translation Services (ITS) This patch adds preliminary support for GICv3 with ARE and SRE, non-secure mode only. It relies on higher exception levels to grant ARE and SRE access. Support for LPI and ITS will be added at a later time. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Zi Shen Lim <zlim@broadcom.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> Reviewed-by: Yun Wu <wuyun.wu@huawei.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com> Tested-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net> 
The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System register for the CPU interfaces (SRE)
- Support for more that 8 CPUs
- Locality-specific Peripheral Interrupts (LPIs)
- Interrupt Translation Services (ITS)

This patch adds preliminary support for GICv3 with ARE and SRE,
non-secure mode only. It relies on higher exception levels to grant ARE
and SRE access.

Support for LPI and ITS will be added at a later time.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Zi Shen Lim <zlim@broadcom.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Reviewed-by: Yun Wu <wuyun.wu@huawei.com>
Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com>
Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com>
Tested-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Acked-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
irqchip: gic: Move some bits of GICv2 to a library-type file 2014-07-08T21:49:14+00:00 Marc Zyngier marc.zyngier@arm.com 2014-06-30T15:01:30+00:00 d51d0af43b30dcae1ca13ea67fd717e03b37f153 A few GICv2 low-level function are actually very useful to GICv3, and it makes some sense to share them across the two drivers. They end-up in their own file, with an additional parameter used to ensure an optional synchronization (unused on GICv2). Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net> 
A few GICv2 low-level function are actually very useful to GICv3,
and it makes some sense to share them across the two drivers.
They end-up in their own file, with an additional parameter used
to ensure an optional synchronization (unused on GICv2).

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1404140510-5382-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
irqchip: or1k-pic: Migrate from arch/openrisc/ 2014-07-01T12:15:06+00:00 Stefan Kristiansson stefan.kristiansson@saunalahti.fi 2014-05-26T20:31:42+00:00 4db8e6d20ccb158de2e06d30a1a421f4d053e429 In addition to consolidating the or1k-pic with other interrupt controllers, this makes OpenRISC less tied to its on-cpu interrupt controller. All or1k-pic specific parts are moved out of irq.c and into drivers/irqchip/irq-or1k-pic.c In that transition, the functionality have been divided into three chip variants. One that handles level triggered interrupts, one that handles edge triggered interrupts and one that handles the interrupt controller that is present in the or1200 OpenRISC cpu implementation. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Link: https://lkml.kernel.org/r/1401136302-27654-1-git-send-email-stefan.kristiansson@saunalahti.fi Acked-by: Jonas Bonn <jonas@southpole.se> Signed-off-by: Jason Cooper <jason@lakedaemon.net> 
In addition to consolidating the or1k-pic with other interrupt
controllers, this makes OpenRISC less tied to its on-cpu
interrupt controller.

All or1k-pic specific parts are moved out of irq.c and into
drivers/irqchip/irq-or1k-pic.c

In that transition, the functionality have been divided into
three chip variants.
One that handles level triggered interrupts, one that handles edge
triggered interrupts and one that handles the interrupt
controller that is present in the or1200 OpenRISC cpu
implementation.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Link: https://lkml.kernel.org/r/1401136302-27654-1-git-send-email-stefan.kristiansson@saunalahti.fi
Acked-by: Jonas Bonn <jonas@southpole.se>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller 2014-05-27T14:43:06+00:00 Florian Fainelli f.fainelli@gmail.com 2014-05-24T00:40:53+00:00 7f646e92766e2070f31dbe542a80b4383918d81d This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using the generic IRQ chip driver with separate enable and disable registers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lkml.kernel.org/r/1400892054-24457-2-git-send-email-f.fainelli@gmail.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> 
This patch adds support for the Level-2 interrupt controller hardware
found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt
controller is implemented using the generic IRQ chip driver with
separate enable and disable registers.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Link: https://lkml.kernel.org/r/1400892054-24457-2-git-send-email-f.fainelli@gmail.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 2014-04-05T22:37:40+00:00 Linus Torvalds torvalds@linux-foundation.org 2014-04-05T22:37:40+00:00 cbda94e039c3862326a65d1d0506447af8330c3c Pull ARM SoC driver changes from Arnd Bergmann: "These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable" * tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac." Revert "net: stmmac: Add SOCFPGA glue driver" ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks ARM: STi: Add reset controller support to mach-sti Kconfig drivers: reset: stih416: add softreset controller drivers: reset: stih415: add softreset controller drivers: reset: Reset controller driver for STiH416 drivers: reset: Reset controller driver for STiH415 drivers: reset: STi SoC system configuration reset controller support dts: socfpga: Add sysmgr node so the gmac can use to reference dts: socfpga: Add support for SD/MMC on the SOCFPGA platform reset: Add optional resets and stubs ARM: shmobile: r7s72100: fix bus clock calculation Power: Reset: Generalize qnap-poweroff to work on Synology devices. dts: socfpga: Update clock entry to support multiple parents ARM: socfpga: Update socfpga_defconfig dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. net: stmmac: Add SOCFPGA glue driver watchdog: orion_wdt: Use %pa to print 'phys_addr_t' drivers: cci: Export CCI PMU revision ... 
Pull ARM SoC driver changes from Arnd Bergmann:
 "These changes are mostly for ARM specific device drivers that either
  don't have an upstream maintainer, or that had the maintainer ask us
  to pick up the changes to avoid conflicts.

  A large chunk of this are clock drivers (bcm281xx, exynos, versatile,
  shmobile), aside from that, reset controllers for STi as well as a
  large rework of the Marvell Orion/EBU watchdog driver are notable"

* tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
  Revert "net: stmmac: Add SOCFPGA glue driver"
  ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks
  ARM: STi: Add reset controller support to mach-sti Kconfig
  drivers: reset: stih416: add softreset controller
  drivers: reset: stih415: add softreset controller
  drivers: reset: Reset controller driver for STiH416
  drivers: reset: Reset controller driver for STiH415
  drivers: reset: STi SoC system configuration reset controller support
  dts: socfpga: Add sysmgr node so the gmac can use to reference
  dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
  reset: Add optional resets and stubs
  ARM: shmobile: r7s72100: fix bus clock calculation
  Power: Reset: Generalize qnap-poweroff to work on Synology devices.
  dts: socfpga: Update clock entry to support multiple parents
  ARM: socfpga: Update socfpga_defconfig
  dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
  net: stmmac: Add SOCFPGA glue driver
  watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
  drivers: cci: Export CCI PMU revision
  ...
Merge tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 2014-04-05T21:19:54+00:00 Linus Torvalds torvalds@linux-foundation.org 2014-04-05T21:19:54+00:00 ff050ad12c551233e546506409c89eb2f640d9f3 Pull ARM SoC specific changes from Arnd Bergmann: "Lots of changes specific to one of the SoC families. Some that stick out are: - mach-qcom gains new features, most importantly SMP support for the newer chips (Stephen Boyd, Rohit Vaswani) - mvebu gains support for three new SoCs: Armada 375, 380 and 385 (Thomas Petazzoni and Free-electrons team) - SMP support for Rockchips (Heiko Stübner) - Lots of i.MX changes (Shawn Guo) - Added support for BCM5301x SoC (Hauke Mehrtens) - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn and Sebastian Hesselbarth doing the final part of a long journey) - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd Bergmann)" * tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits) ARM: sunxi: Select HAVE_ARM_ARCH_TIMER ARM: cache-tauros2: remove ARMv6 code ARM: mvebu: don't select CONFIG_NEON ARM: davinci: fix DT booting with default defconfig ARM: configs: bcm_defconfig: enable bcm590xx regulator support ARM: davinci: remove tnetv107x support MAINTAINERS: Update ARM STi maintainers ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE ARM: bcm21664: Add board support. ARM: sunxi: Add the new watchog compatibles to the reboot code ARM: enable ARM_HAS_SG_CHAIN for multiplatform ARM: davinci: remove da8xx_omapl_defconfig ARM: davinci: da8xx: fix multiple watchdog device registration ARM: davinci: add da8xx specific configs to davinci_all_defconfig ARM: davinci: enable da8xx build concurrently with older devices ARM: BCM5301X: workaround suppress fault ARM: BCM5301X: add early debugging support ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU ARM: mach-bcm: Remove GENERIC_TIME ARM: shmobile: APMU: Fix warnings due to improper printk formats ... 
Pull ARM SoC specific changes from Arnd Bergmann:
 "Lots of changes specific to one of the SoC families.  Some that stick
  out are:

   - mach-qcom gains new features, most importantly SMP support for the
     newer chips (Stephen Boyd, Rohit Vaswani)
   - mvebu gains support for three new SoCs: Armada 375, 380 and 385
     (Thomas Petazzoni and Free-electrons team)
   - SMP support for Rockchips (Heiko Stübner)
   - Lots of i.MX changes (Shawn Guo)
   - Added support for BCM5301x SoC (Hauke Mehrtens)
   - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn
     and Sebastian Hesselbarth doing the final part of a long journey)
   - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd
     Bergmann)"

* tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits)
  ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
  ARM: cache-tauros2: remove ARMv6 code
  ARM: mvebu: don't select CONFIG_NEON
  ARM: davinci: fix DT booting with default defconfig
  ARM: configs: bcm_defconfig: enable bcm590xx regulator support
  ARM: davinci: remove tnetv107x support
  MAINTAINERS: Update ARM STi maintainers
  ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE
  ARM: bcm21664: Add board support.
  ARM: sunxi: Add the new watchog compatibles to the reboot code
  ARM: enable ARM_HAS_SG_CHAIN for multiplatform
  ARM: davinci: remove da8xx_omapl_defconfig
  ARM: davinci: da8xx: fix multiple watchdog device registration
  ARM: davinci: add da8xx specific configs to davinci_all_defconfig
  ARM: davinci: enable da8xx build concurrently with older devices
  ARM: BCM5301X: workaround suppress fault
  ARM: BCM5301X: add early debugging support
  ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU
  ARM: mach-bcm: Remove GENERIC_TIME
  ARM: shmobile: APMU: Fix warnings due to improper printk formats
  ...
ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller 2014-03-26T00:00:50+00:00 Carlo Caione carlo@caione.org 2014-03-19T19:21:17+00:00 6058bb362818e09990de722e983a7f2874e7f61c Allwinner A20/A31 SoCs have special registers to control / (un)mask / acknowledge NMI. This NMI controller is separated and independent from GIC. This patch adds a new irqchip to manage NMI. Signed-off-by: Carlo Caione <carlo@caione.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@googlegroups.com Cc: mark.rutland@arm.com Cc: hdegoede@redhat.com Link: http://lkml.kernel.org/r/1395256879-8475-2-git-send-email-carlo@caione.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de> 
Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.

Signed-off-by: Carlo Caione <carlo@caione.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: mark.rutland@arm.com
Cc: hdegoede@redhat.com
Link: http://lkml.kernel.org/r/1395256879-8475-2-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>