linux-toradex.git/drivers/irqchip/Makefile, branch v6.11-rc3

Merge tag 'irq-msi-2024-07-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2024-07-22T21:02:19+00:00

Pull MSI interrupt updates from Thomas Gleixner:
 "Switch ARM/ARM64 over to the modern per device MSI domains.

  This simplifies the handling of platform MSI and wire to MSI
  controllers and removes about 500 lines of legacy code.

  Aside of that it paves the way for ARM/ARM64 to utilize the dynamic
  allocation of PCI/MSI interrupts and to support the upcoming non
  standard IMS (Interrupt Message Store) mechanism on PCIe devices"

* tag 'irq-msi-2024-07-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  irqchip/gic-v3-its: Correctly fish out the DID for platform MSI
  irqchip/gic-v3-its: Correctly honor the RID remapping
  genirq/msi: Move msi_device_data to core
  genirq/msi: Remove platform MSI leftovers
  irqchip/irq-mvebu-icu: Remove platform MSI leftovers
  irqchip/irq-mvebu-sei: Switch to MSI parent
  irqchip/mvebu-odmi: Switch to parent MSI
  irqchip/mvebu-gicp: Switch to MSI parent
  irqchip/irq-mvebu-icu: Prepare for real per device MSI
  irqchip/imx-mu-msi: Switch to MSI parent
  irqchip/gic-v2m: Switch to device MSI
  irqchip/gic_v3_mbi: Switch over to parent domain
  genirq/msi: Remove platform_msi_create_device_domain()
  irqchip/mbigen: Remove platform_msi_create_device_domain() fallback
  irqchip/gic-v3-its: Switch platform MSI to MSI parent
  irqchip/irq-msi-lib: Prepare for DOMAIN_BUS_WIRED_TO_MSI
  irqchip/mbigen: Prepare for real per device MSI
  irqchip/irq-msi-lib: Prepare for DEVICE MSI to replace platform MSI
  irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X]
  irqchip/irq-msi-lib: Prepare for PCI MSI/MSIX
  ...

irqchip/gic-v3-its: Switch platform MSI to MSI parent

2024-07-18T18:31:20+00:00

Similar to the previous conversion of the PCI/MSI support lift the
prepare() callback from the existing platform MSI code and enable
platform MSI and the related device domain bus tokens in select
and the child domain initialization code.

All platform MSI users are automatically using the new per device MSI model
now.

Signed-off-by: Thomas Gleixner 
Signed-off-by: Anna-Maria Behnsen 
Signed-off-by: Shivamurthy Shastri 
Signed-off-by: Thomas Gleixner 
Link: https://lore.kernel.org/r/20240623142235.271734124@linutronix.de

irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X]

2024-07-18T18:31:20+00:00

The its_pci_msi_prepare() function from the ITS-PCI/MSI code provides the
'global' PCI/MSI domains. Move this function to the ITS-MSI parent code and
amend the function to use the domain hardware size, which is the MSI[X]
vector count, for allocating the ITS slots for the PCI device.

Enable PCI matching in msi_parent_ops and provide the necessary update to
the ITS specific child domain initialization function so that the prepare
callback gets invoked on allocations.

The latter might be optimized to do the allocation right at the point where
the child domain is initialized, but keep it simple for now.

Signed-off-by: Thomas Gleixner 
Signed-off-by: Anna-Maria Behnsen 
Signed-off-by: Shivamurthy Shastri 
Signed-off-by: Thomas Gleixner 
Link: https://lore.kernel.org/r/20240623142235.024567623@linutronix.de

irqchip/gic-v3-its: Provide MSI parent infrastructure

2024-07-18T18:31:19+00:00

To support per device MSI domains the ITS must provide MSI parent domain
functionality.

Provide the basic skeleton for this:

   - msi_parent_ops
   - child domain init callback
   - the MSI parent flag set in irqdomain::flags

This does not make ITS a functional parent domain as there is no bit set in
the bus_select_mask yet, but it provides the base to implement PCI and
platform MSI support gradually on top.

Signed-off-by: Thomas Gleixner 
Signed-off-by: Anna-Maria Behnsen 
Signed-off-by: Shivamurthy Shastri 
Signed-off-by: Thomas Gleixner 
Link: https://lore.kernel.org/r/20240623142234.903076277@linutronix.de

irqchip: Provide irq-msi-lib

2024-07-18T18:31:19+00:00

All irqdomains which provide MSI parent domain functionality for per device
MSI domains need to provide a select() callback for the irqdomain and a
function to initialize the child domain.

Most of these functions would just be copy&paste with minimal
modifications, so provide a library function which implements the required
functionality and is customizable via parent_domain::msi_parent_ops. The
check for the supported bus tokens in msi_lib_init_dev_msi_info() is
expanded step by step within the next patches.

Signed-off-by: Thomas Gleixner 
Signed-off-by: Anna-Maria Behnsen 
Signed-off-by: Shivamurthy Shastri 
Signed-off-by: Thomas Gleixner 
Link: https://lore.kernel.org/r/20240623142234.840975799@linutronix.de

Revert "Loongarch: Support loongarch avec"

2024-06-25T05:40:08+00:00

This reverts commit 760d7e719499d64beea62bfcf53938fb233bb6e7.

This results in build failures and has other issues according to Tianyang.

Reported-by: kernel test robot 
Signed-off-by: Thomas Gleixner 
Cc: Tianyang Zhang 
Closes: https://lore.kernel.org/oe-kbuild-all/202406240451.ygBFNyJ3-lkp@intel.com/

irqchip/stm32-exti: Split MCU and MPU code

2024-06-23T17:49:45+00:00

Keep only the code for ARMv7m STM32 MCUs in in stm32-exti.c and split out
the code for ARMv7a & ARMv8a STM32MPxxx MPUs into stm32mp-exti.c

Signed-off-by: Antonio Borneo 
Signed-off-by: Thomas Gleixner 
Link: https://lore.kernel.org/r/20240620083115.204362-5-antonio.borneo@foss.st.com

Loongarch: Support loongarch avec

2024-06-23T17:09:14+00:00

Introduce the advanced extended interrupt controllers. This feature will
allow each core to have 256 independent interrupt vectors and MSI
interrupts can be independently routed to any vector on any CPU.

[ tglx: Fixed up coding style. Made on/offline functions void ]

Co-developed-by: Jianmin Lv 
Signed-off-by: Jianmin Lv 
Co-developed-by: Liupu Wang 
Signed-off-by: Liupu Wang 
Signed-off-by: Tianyang Zhang 
Signed-off-by: Thomas Gleixner 
Link: https://lore.kernel.org/r/20240604125026.18745-1-zhangtianyang@loongson.cn

irqchip: Add support for LAN966x OIC

2024-06-17T13:48:15+00:00

The Microchip LAN966x outband interrupt controller (OIC) maps the
internal interrupt sources of the LAN966x device to an external
interrupt.
When the LAN966x device is used as a PCI device, the external interrupt
is routed to the PCI interrupt.

Signed-off-by: Herve Codina 
Signed-off-by: Thomas Gleixner 
Link: https://lore.kernel.org/r/20240614173232.1184015-23-herve.codina@bootlin.com

irqchip/riscv-aplic: Add support for MSI-mode

2024-03-25T16:38:29+00:00

The RISC-V advanced platform-level interrupt controller (APLIC) has
two modes of operation: 1) Direct mode and 2) MSI mode.
(For more details, refer https://github.com/riscv/riscv-aia)

In APLIC MSI-mode, wired interrupts are forwared as message signaled
interrupts (MSIs) to CPUs via IMSIC.

Extend the existing APLIC irqchip driver to support MSI-mode for
RISC-V platforms having both wired interrupts and MSIs.

Signed-off-by: Anup Patel 
Signed-off-by: Thomas Gleixner 
Tested-by: Björn Töpel 
Reviewed-by: Björn Töpel 
Link: https://lore.kernel.org/r/20240307140307.646078-8-apatel@ventanamicro.com