linux-toradex.git/drivers/irqchip, branch master Linux kernel for Apalis and Colibri modules irqchip/irq-realtek-rtl: Add multicore support 2026-06-05T09:35:10+00:00 Markus Stockhausen markus.stockhausen@gmx.de 2026-06-04T18:25:06+00:00 a1a35c09241f0577cc40f65d7372fed01138619d The Realtek interrupt driver currently supports only single core systems. So the higher end devices like RTL839x and RTL930x with dual VPEs must be driven with NR_CPU=1. Enhance the driver to support multicore (dual VPE) systems. For this: - Extend the register map for multiple cores - Search for multiple CPU cores in the devicetree - Improve the register helpers to support multiple cores - Add an affinity setter - Enhance the IRQ handler for multiple cores Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260604182506.1113440-3-markus.stockhausen@gmx.de 
The Realtek interrupt driver currently supports only single core
systems. So the higher end devices like RTL839x and RTL930x with
dual VPEs must be driven with NR_CPU=1. Enhance the driver to
support multicore (dual VPE) systems. For this:

  - Extend the register map for multiple cores
  - Search for multiple CPU cores in the devicetree
  - Improve the register helpers to support multiple cores
  - Add an affinity setter
  - Enhance the IRQ handler for multiple cores

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260604182506.1113440-3-markus.stockhausen@gmx.de
irqchip/irq-realtek-rtl: Add/simplify register helpers 2026-06-05T09:35:10+00:00 Markus Stockhausen markus.stockhausen@gmx.de 2026-06-04T18:25:05+00:00 167883f75f83088a2b32c85ce5e3d0cd1cef157b The Realtek interrupt controller has two important registers that are used by the driver in several places - GIMR: global interrupt mask register - IRR: Interrupt routing registers The usage of these registers is very inconsistent. GIMR is addressed directly while IRR has a helper that needs a macro as an input. Harmonize this by providing consistent helpers that improve code readability. The callers of these helpers use classic lock/unlock functions and sometimes use the wrong locking helper. E.g. irqsave variants are used in mask/unmask although not needed. Adapt and fix the surrounding call locations. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260604182506.1113440-2-markus.stockhausen@gmx.de 
The Realtek interrupt controller has two important registers that are used
by the driver in several places

 - GIMR: global interrupt mask register
 - IRR: Interrupt routing registers

The usage of these registers is very inconsistent. GIMR is addressed
directly while IRR has a helper that needs a macro as an input. Harmonize
this by providing consistent helpers that improve code readability.

The callers of these helpers use classic lock/unlock functions and
sometimes use the wrong locking helper. E.g. irqsave variants are used in
mask/unmask although not needed. Adapt and fix the surrounding call
locations.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260604182506.1113440-2-markus.stockhausen@gmx.de
irqchip/loongarch-ir: Add IR (interrupt redirection) irqchip support 2026-06-03T20:28:11+00:00 Tianyang Zhang zhangtianyang@loongson.cn 2026-05-13T01:28:35+00:00 71619266e0a272ef5ef137a661e8e3f1711c2aba The main function of the redirect interrupt controller is to manage the redirected-interrupt table, which consists of many redirected entries. When MSI interrupts are requested, the driver creates a corresponding redirected entry that describes the target CPU/vector number and the operating mode of the interrupt. The redirected interrupt module has an independent cache, and during the interrupt routing process, it will prioritize the redirected entries that hit the cache. The irqchip driver can invalidate certain entry caches via a command queue. Co-developed-by: Liupu Wang <wangliupu@loongson.cn> Signed-off-by: Liupu Wang <wangliupu@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/20260513012839.2856463-5-zhangtianyang@loongson.cn 
The main function of the redirect interrupt controller is to manage
the redirected-interrupt table, which consists of many redirected entries.

When MSI interrupts are requested, the driver creates a corresponding
redirected entry that describes the target CPU/vector number and the
operating mode of the interrupt. The redirected interrupt module has an
independent cache, and during the interrupt routing process, it will
prioritize the redirected entries that hit the cache. The irqchip driver
can invalidate certain entry caches via a command queue.

Co-developed-by: Liupu Wang <wangliupu@loongson.cn>
Signed-off-by: Liupu Wang <wangliupu@loongson.cn>
Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
Link: https://patch.msgid.link/20260513012839.2856463-5-zhangtianyang@loongson.cn
irqchip/loongarch-avec: Return IRQ_SET_MASK_OK_DONE when keep affinity 2026-06-03T20:28:11+00:00 Tianyang Zhang zhangtianyang@loongson.cn 2026-05-13T01:28:34+00:00 d9ba741cd168649a768e9f95fe9db3d3596a6ae6 Interrupt redirection support requires a new redirect domain, which will appear as a child domain of avecintc domain. For each interrupt source, avecintc domain only provides the CPU/interrupt vectors, while redirect domain provides other operations to synchronize the interrupt affinity information among multiple cores. When modifying the affinity of an interrupt associated with the redirect domain, if the avecintc domain detects that the actual interrupt affinity hasn't been changed, then the redirect domain doesn't need to perform any operations. To achieve the above purpose, in avecintc_set_affinity() when the current affinity remains valid, then return value is set to IRQ_SET_MASK_OK_DONE. This doesn't introduce any compatibility issues, even if the new return value causing msi_domain_set_affinity() to no longer perform the call to irq_chip_write_msi_msg(): 1) When both avecintc and redirect exist in the system, the msg_address and msg_data no longer change after the allocation phase, so it does not actually require updating the MSI message info. 2) When only avecintc exists in the system, the irq_domain_activate_irq() interface will be responsible for the initial configuration of the MSI message info, which is unconditional. After that, if unnecessary, there is no modification to the MSI message info. Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/20260513012839.2856463-4-zhangtianyang@loongson.cn 
Interrupt redirection support requires a new redirect domain, which will
appear as a child domain of avecintc domain. For each interrupt source,
avecintc domain only provides the CPU/interrupt vectors, while redirect
domain provides other operations to synchronize the interrupt affinity
information among multiple cores.

When modifying the affinity of an interrupt associated with the redirect
domain, if the avecintc domain detects that the actual interrupt affinity
hasn't been changed, then the redirect domain doesn't need to perform any
operations.

To achieve the above purpose, in avecintc_set_affinity() when the current
affinity remains valid, then return value is set to IRQ_SET_MASK_OK_DONE.

This doesn't introduce any compatibility issues, even if the new return
value causing msi_domain_set_affinity() to no longer perform the call to
irq_chip_write_msi_msg():

  1) When both avecintc and redirect exist in the system, the msg_address
     and msg_data no longer change after the allocation phase, so it does
     not actually require updating the MSI message info.

  2) When only avecintc exists in the system, the irq_domain_activate_irq()
     interface will be responsible for the initial configuration of the MSI
     message info, which is unconditional. After that, if unnecessary,
     there is no modification to the MSI message info.

Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
Link: https://patch.msgid.link/20260513012839.2856463-4-zhangtianyang@loongson.cn
irqchip/loongarch-avec: Prepare for interrupt redirection support 2026-06-03T20:28:11+00:00 Tianyang Zhang zhangtianyang@loongson.cn 2026-05-13T01:28:33+00:00 4b522d3cf4777531023c6d18679ab5a5d3552c04 Interrupt redirection support requires a new interrupt chip, which needs to share data structures, constants and functions with the AVECINTC code. So move them to the header file and make the required functions public. Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/20260513012839.2856463-3-zhangtianyang@loongson.cn 
Interrupt redirection support requires a new interrupt chip, which needs
to share data structures, constants and functions with the AVECINTC code.

So move them to the header file and make the required functions public.

Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
Link: https://patch.msgid.link/20260513012839.2856463-3-zhangtianyang@loongson.cn
irqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit position 2026-06-03T16:27:06+00:00 Mukesh Ojha mukesh.ojha@oss.qualcomm.com 2026-05-27T09:54:26+00:00 8766c87e9bb499b5e2b04b9f51f9e525d41c5b46 The IRQ_ENABLE_BANK register is a bank of 32-bit words where each bit represents one PDC pin. The bank index and bit position within the bank are encoded in the flat pin number as bits [31:5] and [4:0] respectively. Replace the open-coded division and modulo with FIELD_GET() and GENMASK() to make the bit extraction self-documenting and consistent with the FIELD_PREP() style already used in the PDC_VERSION() macro. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260527095426.2324504-5-mukesh.ojha@oss.qualcomm.com 
The IRQ_ENABLE_BANK register is a bank of 32-bit words where each bit
represents one PDC pin. The bank index and bit position within the bank
are encoded in the flat pin number as bits [31:5] and [4:0] respectively.

Replace the open-coded division and modulo with FIELD_GET() and GENMASK()
to make the bit extraction self-documenting and consistent with the
FIELD_PREP() style already used in the PDC_VERSION() macro.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260527095426.2324504-5-mukesh.ojha@oss.qualcomm.com
irqchip/qcom-pdc: Add PDC_VERSION() macro to describe version register fields 2026-06-03T16:27:05+00:00 Mukesh Ojha mukesh.ojha@oss.qualcomm.com 2026-05-27T09:54:25+00:00 ef631c422f2cc3f5a8c0687364bfafec4f3d531c The PDC hardware version register encodes major, minor and step fields in byte-sized fields at bits [23:16], [15:8] and [7:0] respectively. The existing PDC_VERSION_3_2 constant was a bare magic number (0x30200) with no indication of this encoding. Add GENMASK-based field definitions for each sub-field and a PDC_VERSION(maj, min, step) constructor macro using FIELD_PREP, making the encoding self-documenting. Replace the magic constant with PDC_VERSION(3, 2, 0). Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260527095426.2324504-4-mukesh.ojha@oss.qualcomm.com 
The PDC hardware version register encodes major, minor and step fields
in byte-sized fields at bits [23:16], [15:8] and [7:0] respectively.
The existing PDC_VERSION_3_2 constant was a bare magic number (0x30200)
with no indication of this encoding.

Add GENMASK-based field definitions for each sub-field and a
PDC_VERSION(maj, min, step) constructor macro using FIELD_PREP, making
the encoding self-documenting. Replace the magic constant with
PDC_VERSION(3, 2, 0).

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260527095426.2324504-4-mukesh.ojha@oss.qualcomm.com
irqchip/qcom-pdc: Tighten ioremap clamp to single DRV region size 2026-06-03T16:27:05+00:00 Mukesh Ojha mukesh.ojha@oss.qualcomm.com 2026-05-27T09:54:24+00:00 f1a5a0f4c0eab83299201129cffb7907d7dc99c6 The QCOM_PDC_SIZE constant (0x30000) was introduced to work around old sm8150 DTs that described a too-small PDC register region, causing the driver to silently expand the ioremap to cover three DRV regions. Now that the preceding DT fixes have corrected all platforms to describe only the APSS DRV region (0x10000), the oversized clamp is no longer needed. Replace QCOM_PDC_SIZE with PDC_DRV_SIZE (0x10000) in the clamp so the minimum mapped size matches a single DRV region. The clamp and warning are intentionally kept to preserve backward compatibility with any old DTs that may still describe a smaller region. While at it, rename PDC_DRV_OFFSET to PDC_DRV_SIZE since the constant represents the size of a DRV region and is used as both the ioremap minimum size and the offset to the previous DRV region. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20260527095426.2324504-3-mukesh.ojha@oss.qualcomm.com 
The QCOM_PDC_SIZE constant (0x30000) was introduced to work around old
sm8150 DTs that described a too-small PDC register region, causing the
driver to silently expand the ioremap to cover three DRV regions. Now
that the preceding DT fixes have corrected all platforms to describe only
the APSS DRV region (0x10000), the oversized clamp is no longer needed.

Replace QCOM_PDC_SIZE with PDC_DRV_SIZE (0x10000) in the clamp so the
minimum mapped size matches a single DRV region. The clamp and warning
are intentionally kept to preserve backward compatibility with any old
DTs that may still describe a smaller region.

While at it, rename PDC_DRV_OFFSET to PDC_DRV_SIZE since the constant
represents the size of a DRV region and is used as both the ioremap
minimum size and the offset to the previous DRV region.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260527095426.2324504-3-mukesh.ojha@oss.qualcomm.com
irqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpers 2026-06-03T16:27:05+00:00 Mukesh Ojha mukesh.ojha@oss.qualcomm.com 2026-05-27T09:54:23+00:00 668f3382845b3751220c6fcdd4c4cda0c2f0c78f The __pdc_enable_intr() function contains a version branch that selects between two distinct enable mechanisms: a bank-based IRQ_ENABLE_BANK register for HW < 3.2, and a per-pin enable bit in IRQ_i_CFG for HW >= 3.2. These two paths share no code and serve different hardware. Split them into two focused static functions: pdc_enable_intr_bank() for HW < 3.2 and pdc_enable_intr_cfg() for HW >= 3.2. No functional change. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260527095426.2324504-2-mukesh.ojha@oss.qualcomm.com 
The __pdc_enable_intr() function contains a version branch that selects
between two distinct enable mechanisms: a bank-based IRQ_ENABLE_BANK
register for HW < 3.2, and a per-pin enable bit in IRQ_i_CFG for
HW >= 3.2. These two paths share no code and serve different hardware.

Split them into two focused static functions: pdc_enable_intr_bank()
for HW < 3.2 and pdc_enable_intr_cfg() for HW >= 3.2. No functional
change.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260527095426.2324504-2-mukesh.ojha@oss.qualcomm.com
irqchip/exynos-combiner: Remove useless spinlock 2026-06-03T16:27:05+00:00 Marek Szyprowski m.szyprowski@samsung.com 2026-05-22T06:10:12+00:00 6fe450074626eaab3def4b3e8c1819d46d2d682c irq_controller_lock doesn't protect anything, it is a leftover from early development or copy/paste. Remove it completely. Fixes: 96031b31a4b3 ("irqchip/exynos-combiner: Switch to raw_spinlock") Suggested-by: Thomas Gleixner <tglx@kernel.org> Suggested-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/all/20260521090453.bbUZ00tS@linutronix.de Link: https://patch.msgid.link/20260522061012.2687122-1-m.szyprowski@samsung.com/ 
irq_controller_lock doesn't protect anything, it is a leftover from early
development or copy/paste. Remove it completely.

Fixes: 96031b31a4b3 ("irqchip/exynos-combiner: Switch to raw_spinlock")
Suggested-by: Thomas Gleixner <tglx@kernel.org>
Suggested-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/all/20260521090453.bbUZ00tS@linutronix.de
Link: https://patch.msgid.link/20260522061012.2687122-1-m.szyprowski@samsung.com/