linux-toradex.git/drivers/irqchip, branch v3.14.9

irqchip: armada-370-xp: Fix releasing of MSIs

2014-06-07T17:28:13+00:00

commit ff3c664505bf8a8334bca5045e87b85cfe4d2277 upstream.

Store the value of d->hwirq in a local variable as the real value is wiped out
by calling irq_dispose_mapping. Without this patch, the armada_370_xp_free_msi
function would always free MSI#0, no matter what was passed to it.

Fixes: 31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4 ('irqchip: armada-370-xp: implement MSI support')
Signed-off-by: Neil Greatorex 
Link: https://lkml.kernel.org/r/1397823593-1932-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni 
Link: https://lkml.kernel.org/r/1397823593-1932-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper 
Signed-off-by: Greg Kroah-Hartman

irqchip: armada-370-xp: implement the ->check_device() msi_chip operation

2014-06-07T17:28:12+00:00

commit 830cbe4b7a918613276aa3d3b28d24410623f92c upstream.

Until now, we were leaving the ->check_device() msi_chip operation
empty, which leads the PCI core to believe that we support both MSI
and MSI-X. In fact, we do not support MSI-X, so we have to tell this
to the PCI core by providing an implementation of this operation.

Fixes: 31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4 ('irqchip: armada-370-xp: implement MSI support')
Signed-off-by: Thomas Petazzoni 
Link: https://lkml.kernel.org/r/1397823593-1932-3-git-send-email-thomas.petazzoni@free-electrons.com
Tested-by: Neil Greatorex 
Signed-off-by: Jason Cooper 
Signed-off-by: Greg Kroah-Hartman

irqchip: armada-370-xp: fix invalid cast of signed value into unsigned variable

2014-06-07T17:28:12+00:00

commit da343fc776e0bcb238b65d9d24610819b95d0ef4 upstream.

The armada_370_xp_alloc_msi() function returns a signed int, which is
negative on error. However, we store the return value into an
irq_hw_number_t, which is unsigned. Therefore, we actually never test
if armada_370_xp_alloc_msi() returns an error or not, which may lead
us to use hwirq numbers of as 0xffffffe4 (when
armada_370_xp_alloc_msi() returns -ENOSPC).

This commit fixes that by storing the return value of
armada_370_xp_alloc_msi() in a signed variable.

Fixes: 31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4 ('irqchip: armada-370-xp: implement MSI support')
Signed-off-by: Thomas Petazzoni 
Link: https://lkml.kernel.org/r/1397823593-1932-2-git-send-email-thomas.petazzoni@free-electrons.com
Tested-by: Neil Greatorex 
Signed-off-by: Jason Cooper 
Signed-off-by: Greg Kroah-Hartman

irqchip: Gic: Support forced affinity setting

2014-06-07T17:28:07+00:00

commit ffde1de64012c406dfdda8690918248b472f24e4 upstream.

To support the affinity setting of per cpu timers in the early startup
of a not yet online cpu, implement the force logic, which disables the
cpu online check.

Tagged for stable to allow a simple fix of the affected SoC clock
event drivers.

Signed-off-by: Thomas Gleixner 
Tested-by: Krzysztof Kozlowski 
Cc: Kyungmin Park 
Cc: Marek Szyprowski 
Cc: Bartlomiej Zolnierkiewicz 
Cc: Tomasz Figa ,
Cc: Daniel Lezcano ,
Cc: Kukjin Kim 
Cc: linux-arm-kernel@lists.infradead.org,
Link: http://lkml.kernel.org/r/20140416143315.916984416@linutronix.de
Signed-off-by: Thomas Gleixner 
Signed-off-by: Greg Kroah-Hartman

irq-metag*: stop set_affinity vectoring to offline cpus

2014-02-25T22:35:06+00:00

Fix irq_set_affinity callbacks in the Meta IRQ chip drivers to AND
cpu_online_mask into the cpumask when picking a CPU to vector the
interrupt to.

As Thomas pointed out, the /proc/irq/$N/smp_affinity interface doesn't
filter out offline CPUs, so without this patch if you offline CPU0 and
set an IRQ affinity to 0x3 it vectors the interrupt onto CPU0 even
though it is offline.

Reported-by: Thomas Gleixner 
Signed-off-by: James Hogan 
Cc: Thomas Gleixner 
Cc: linux-metag@vger.kernel.org
Cc: stable@vger.kernel.org

Merge tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu into irq/urgent

2014-02-21T22:57:33+00:00

irqchip mvebu fixes for v3.14

 - orion:
    - fixes for clearing bridge cause register, and clearing stale interrupts

Signed-off-by: Thomas Gleixner

irqchip: orion: Fix getting generic chip pointer.

2014-02-21T21:46:56+00:00

Enabling SPARSE_IRQ shows up a bug in the irq-orion bridge interrupt
handler. The bridge interrupt is implemented using a single generic
chip. Thus the parameter passed to irq_get_domain_generic_chip()
should always be zero.

Signed-off-by: Andrew Lunn 
Acked-by: Sebastian Hesselbarth 
Fixes: 9dbd90f17e4f ("irqchip: Add support for Marvell Orion SoCs")
Cc:  # v3.11+
Signed-off-by: Jason Cooper

irqchip: orion: clear stale interrupts in irq_startup

2014-02-06T18:03:32+00:00

Bridge IRQ_CAUSE bits are asserted regardless of the corresponding bit in
IRQ_MASK register. To avoid interrupt events on stale irqs, we have to clear
them before unmask. This installs an .irq_startup callback to ensure stale
irqs are cleared before initial unmask.

Signed-off-by: Sebastian Hesselbarth 
Tested-by: Ezequiel Garcia 
Cc: : f56c0738b5c2: "irqchip: orion: clear bridge cause register on init"
Cc: : 38bd80b84fca: "irqchip: orion: use handle_edge_irq on bridge irqs"
Cc:  # v3.10+
Signed-off-by: Jason Cooper

irqchip: orion: use handle_edge_irq on bridge irqs

2014-02-06T18:03:22+00:00

Bridge irqs are edge-triggered, i.e. they get asserted on low-to-high
transitions and not on the level of the downstream interrupt line.
This replaces handle_level_irq by the more appropriate handle_edge_irq.

Signed-off-by: Sebastian Hesselbarth 
Tested-by: Ezequiel Garcia 
Cc: : f56c0738b5c2: "irqchip: orion: clear bridge cause register on init"
Cc:  # v3.10+
Signed-off-by: Jason Cooper

irqchip: orion: clear bridge cause register on init

2014-02-06T18:03:08+00:00

It is good practice to mask and clear pending irqs on init. We already
mask all irqs, so also clear the bridge irq cause register.

Signed-off-by: Sebastian Hesselbarth 
Tested-by: Ezequiel Garcia 
Cc:  # v3.10+
Signed-off-by: Jason Cooper