<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/drivers/mailbox/imx-mailbox.c, branch v5.2-rc7</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>mailbox: imx: use devm_platform_ioremap_resource() to simplify code</title>
<updated>2019-05-09T05:40:49+00:00</updated>
<author>
<name>Anson Huang</name>
<email>anson.huang@nxp.com</email>
</author>
<published>2019-04-01T05:15:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0c40e631cd7f1dd762869bc91550ab20381d87bf'/>
<id>0c40e631cd7f1dd762869bc91550ab20381d87bf</id>
<content type='text'>
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.

Signed-off-by: Anson Huang &lt;Anson.Huang@nxp.com&gt;
Reviewed-by: Mukesh Ojha &lt;mojha@codeaurora.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.

Signed-off-by: Anson Huang &lt;Anson.Huang@nxp.com&gt;
Reviewed-by: Mukesh Ojha &lt;mojha@codeaurora.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mailbox: imx: keep MU irq working during suspend/resume</title>
<updated>2019-03-11T07:51:43+00:00</updated>
<author>
<name>Anson Huang</name>
<email>anson.huang@nxp.com</email>
</author>
<published>2019-02-12T12:40:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=17b860bbfc844a3d8e38135ef430d4af8e436b9e'/>
<id>17b860bbfc844a3d8e38135ef430d4af8e436b9e</id>
<content type='text'>
During noirq suspend phase, mailbox MU irq will be masked
but many drivers still need to communicate with system
controller firmware via mailbox, if MU irq is masked, it
will cause RPC timeout as below:

[   23.372103] imx-scu scu: RPC send msg timeout

Setting MU irq to be wakeup source is NOT working as GIC
driver does NOT have .irq_set_wake implemented, so to
support suspend/resume, just make imx mailbox driver NOT
suspend, since MU is always a wakeup source on i.MX platforms
with system controller inside, and its power/clock is
maintained by system controller, mailbox driver no need
to manage them.

Signed-off-by: Anson Huang &lt;Anson.Huang@nxp.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
During noirq suspend phase, mailbox MU irq will be masked
but many drivers still need to communicate with system
controller firmware via mailbox, if MU irq is masked, it
will cause RPC timeout as below:

[   23.372103] imx-scu scu: RPC send msg timeout

Setting MU irq to be wakeup source is NOT working as GIC
driver does NOT have .irq_set_wake implemented, so to
support suspend/resume, just make imx mailbox driver NOT
suspend, since MU is always a wakeup source on i.MX platforms
with system controller inside, and its power/clock is
maintained by system controller, mailbox driver no need
to manage them.

Signed-off-by: Anson Huang &lt;Anson.Huang@nxp.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mailbox: imx: Use device-managed registration API</title>
<updated>2018-12-21T22:49:25+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-12-20T17:19:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4013286c7231e05780c6e73b91d357678f819b4b'/>
<id>4013286c7231e05780c6e73b91d357678f819b4b</id>
<content type='text'>
Get rid of some boilerplate driver removal code by using the newly added
device-managed registration API.

Reviewed-by: Oleksij Rempel &lt;o.rempel@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Get rid of some boilerplate driver removal code by using the newly added
device-managed registration API.

Reviewed-by: Oleksij Rempel &lt;o.rempel@pengutronix.de&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mailbox: Add support for i.MX messaging unit</title>
<updated>2018-08-15T04:23:07+00:00</updated>
<author>
<name>Oleksij Rempel</name>
<email>o.rempel@pengutronix.de</email>
</author>
<published>2018-08-03T05:29:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2bb7005696e2246baa88772341ca032ff09a63cb'/>
<id>2bb7005696e2246baa88772341ca032ff09a63cb</id>
<content type='text'>
The i.MX Messaging Unit is a two side block which allows applications
implement communication over this sides.

The MU includes the following features:
- Messaging control by interrupts or by polling
- Four general-purpose interrupt requests reflected to the other side
- Three general-purpose flags reflected to the other side
- Four receive registers with maskable interrupt
- Four transmit registers with maskable interrupt

Reviewed-by: Vladimir Zapolskiy &lt;vz@mleia.com&gt;
Reviewed-by: Dong Aisheng &lt;aisheng.dong@nxp.com&gt;
Signed-off-by: Oleksij Rempel &lt;o.rempel@pengutronix.de&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The i.MX Messaging Unit is a two side block which allows applications
implement communication over this sides.

The MU includes the following features:
- Messaging control by interrupts or by polling
- Four general-purpose interrupt requests reflected to the other side
- Three general-purpose flags reflected to the other side
- Four receive registers with maskable interrupt
- Four transmit registers with maskable interrupt

Reviewed-by: Vladimir Zapolskiy &lt;vz@mleia.com&gt;
Reviewed-by: Dong Aisheng &lt;aisheng.dong@nxp.com&gt;
Signed-off-by: Oleksij Rempel &lt;o.rempel@pengutronix.de&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
