linux-toradex.git/drivers/memory/omap-gpmc.c, branch v4.7-rc4

memory: omap-gpmc: Fix omap gpmc EXTRADELAY timing

2016-06-16T08:43:48+00:00

In the omap gpmc driver it can be noticed that GPMC_CONFIG4_OEEXTRADELAY
is overwritten by the WEEXTRADELAY value from the device tree and
GPMC_CONFIG4_WEEXTRADELAY is not updated by the value from the device
tree.

As a consequence, the memory accesses cannot be configured properly when
the extra delay are needed for OE and WE.

Fix the update of GPMC_CONFIG4_WEEXTRADELAY with the value from the
device tree file and prevents GPMC_CONFIG4_OEXTRADELAY
being overwritten by the WEXTRADELAY value from the device tree.

Cc: stable@vger.kernel.org
Signed-off-by: Ocquidant, Sebastien 
Signed-off-by: Roger Quadros

mtd: nand: omap2: rely on generic DT parsing done in nand_scan_ident()

2016-04-19T20:04:54+00:00

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.

Signed-off-by: Boris Brezillon 
Acked-by: Roger Quadros 
Tested-by: Franklin S Cooper Jr.

memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via gpmc_regs

2016-04-15T08:55:28+00:00

GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.

They must use gpmc_omap_get_nand_ops() instead.

Signed-off-by: Roger Quadros 
Acked-by: Tony Lindgren

memory: omap-gpmc: Support WAIT pin edge interrupts

2016-04-15T08:55:06+00:00

OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered
interrupts if not used for memory wait state insertion.

Support these interrupts via the gpmc IRQ domain.

The gpmc IRQ domain interrupt map is:

0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 edge
3 - GPMC_WAIT1 edge, and so on

Signed-off-by: Roger Quadros 
Acked-by: Rob Herring 
Acked-by: Tony Lindgren

memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring

2016-04-15T08:55:00+00:00

If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.

Signed-off-by: Roger Quadros 
Acked-by: Tony Lindgren

memory: omap-gpmc: Support general purpose input for WAITPINs

2016-04-15T08:54:12+00:00

OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.

The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.

Signed-off-by: Roger Quadros 
Acked-by: Rob Herring 
Acked-by: Tony Lindgren

memory: omap-gpmc: Prevent mapping into 1st 16MB

2016-04-15T08:53:54+00:00

We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.

Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.

Signed-off-by: Roger Quadros 
Acked-by: Tony Lindgren

mtd: nand: omap: Clean up device tree support

2016-04-15T08:53:36+00:00

Move NAND specific device tree parsing to NAND driver.

The NAND controller node must have a compatible id, register space
resource and interrupt resource.

Signed-off-by: Roger Quadros 
Acked-by: Brian Norris 
Acked-by: Tony Lindgren

memory: omap-gpmc: Implement IRQ domain for NAND IRQs

2016-04-15T08:52:28+00:00

GPMC provides 2 interrupts for NAND use. i.e. fifoevent and termcount.
Use IRQ domain for this. NAND device tree node can then
get the necessary interrupts by using gpmc as the interrupt parent.

Legacy boot uses gpmc_get_client_irq to get the
NAND interrupts from the GPMC IRQ domain.
Get rid of custom bitmasks and use IRQ domain for that
as well.

Signed-off-by: Roger Quadros 
Acked-by: Rob Herring 
Acked-by: Tony Lindgren

memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status

2016-04-15T08:51:57+00:00

This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.

Signed-off-by: Roger Quadros 
Acked-by: Tony Lindgren