linux-toradex.git/drivers/mfd/lpc_ich.c, branch v6.6-rc1

mfd: Move from strlcpy with unused retval to strscpy

2022-09-28T15:17:39+00:00

Follow the advice of the below link and prefer 'strscpy' in this
subsystem. Conversion is 1:1 because the return value is not used.
Generated by a coccinelle script.

Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/
Signed-off-by: Wolfram Sang 
Signed-off-by: Lee Jones 
Link: https://lore.kernel.org/r/20220818210030.7012-1-wsa+renesas@sang-engineering.com

mfd: lpc_ich: Add support for pinctrl in non-ACPI system

2022-07-14T09:50:31+00:00

Add support for non-ACPI systems, such as system that uses
Advanced Boot Loader (ABL) whereby a platform device has to be created
in order to bind with pin control and GPIO.

At the moment, Intel Apollo Lake In-Vehicle Infotainment (IVI) system
requires a driver to hide and unhide P2SB to lookup P2SB BAR and pass
the PCI BAR address to GPIO.

Signed-off-by: Tan Jui Nee 
Co-developed-by: Andy Shevchenko 
Signed-off-by: Andy Shevchenko 
Tested-by: Henning Schild 
Acked-by: Hans de Goede 
Acked-by: Linus Walleij 
Signed-off-by: Lee Jones

mfd: lpc_ich: Switch to generic p2sb_bar()

2022-07-14T09:50:25+00:00

Instead of open coding p2sb_bar() functionality we are going to
use generic library. There is one more user en route.

This is more than just a clean-up. It also fixes a potential issue
seen when SPI BAR is 64-bit. The current code works if and only if
the PCI BAR of the hidden device is inside 4G address space. In case
when firmware decides to go above 4G, we will get a wrong address.

Signed-off-by: Andy Shevchenko 
Tested-by: Henning Schild 
Acked-by: Hans de Goede 
Acked-by: Linus Walleij 
Signed-off-by: Lee Jones

mfd: lpc_ich: Factor out lpc_ich_enable_spi_write()

2022-07-14T09:50:14+00:00

Factor out duplicate code to lpc_ich_enable_spi_write() helper function.

Signed-off-by: Andy Shevchenko 
Tested-by: Henning Schild 
Acked-by: Hans de Goede 
Acked-by: Linus Walleij 
Signed-off-by: Lee Jones

mtd: spi-nor: intel-spi: Disable write protection only if asked

2022-02-14T12:53:08+00:00

Currently the driver tries to disable the BIOS write protection
automatically even if this is not what the user wants. For this reason
modify the driver so that by default it does not touch the write
protection. Only if specifically asked by the user (setting writeable=1
command line parameter) the driver tries to disable the BIOS write
protection.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Mauro Lima 
Reviewed-by: Tudor Ambarus 
Acked-by: Lee Jones 
Link: https://lore.kernel.org/r/20220209122706.42439-2-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown

mfd: lpc_ich: Enable GPIO driver for DH89xxCC

2021-07-20T14:46:51+00:00

Based on the Intel Datasheet for the DH89xxCC PCH, the GPIO driver
is the same as ICH_v5_GPIO, minus the fact the DH89xxCC also has
blink support. However, blink support isn't supported by the GPIO
driver so we should use ICH_v5_GPIO. Tested and working on a Meraki
MX100-HW.

Signed-off-by: Chris Blake 
Co-developed-by: Christian Lamparter 
Signed-off-by: Lee Jones

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 294

2019-06-05T15:36:38+00:00

Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license 2 as published
  by the free software foundation this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation this program is distributed in the hope
  that it [would] be useful but without any warranty without even the
  implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 9 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Reviewed-by: Alexios Zavras 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141901.804956444@linutronix.de
Signed-off-by: Greg Kroah-Hartman

mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Apollo Lake

2018-01-08T11:03:35+00:00

Just to be on the safe side, don't touch the bit. If write access to the
flash chip is needed, the BIOS needs to enable it explicitly.

Signed-off-by: Mika Westerberg 
Signed-off-by: Lee Jones

mfd: lpc_ich: Avoton/Rangeley uses SPI_BYT method

2017-10-24T08:12:03+00:00

Avoton/Rangeley are based on Silvermount micro-architecture, like
Bay Trail, and uses the INTEL_SPI_BYT method to drive SPI.

Cc: stable@vger.kernel.org
Signed-off-by: Joakim Tjernlund 
Acked-by: Mika Westerberg 
Signed-off-by: Lee Jones

mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/Broadwell

2017-09-05T07:46:01+00:00

At least on Lenovo Thinkpad Yoga, the BIOS seems to monitor the SPI-NOR
write protection bit and if it is flipped to read/write it assumes the
BIOS configuration was changed on next reboot. It then, for unknown
reasons, resets the BIOS settings back to default.

We can prevent this by just leaving the write protection bit intact and
let the SPI-NOR driver know whether the device is writable or not. In
case of this particular Lenovo the SPI-NOR flash will be exposed as
read-only.

Fixes: ff00d7a32a1b ("mfd: lpc_ich: Add support for SPI serial flash host controller")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=195951
Reported-by: Abdó Roig-Marange 
Signed-off-by: Mika Westerberg 
Signed-off-by: Lee Jones