linux-toradex.git/drivers/mfd/rts5249.c, branch v4.1 Linux kernel for Apalis and Colibri modules mfd: rtsx: Using pcr_dbg replace dev_dbg 2015-03-03T16:41:21+00:00 Micky Ching micky_ching@realsil.com.cn 2015-02-25T05:50:16+00:00 0523b8f41473c3d869adebeb029b5dc045ab35d8 pcr_dbg is a wrapper of dev_dbg, which can save some code, and help to enable/disable debug message static. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
pcr_dbg is a wrapper of dev_dbg, which can save some code,
and help to enable/disable debug message static.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: rtsx: Add support for rts525A 2015-03-03T16:41:21+00:00 Micky Ching micky_ching@realsil.com.cn 2015-02-25T05:50:15+00:00 41bc2334737a32d3062a318dde5964590d0e24c9 Add support for new chip rts525A. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
Add support for new chip rts525A.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: rtsx: Add support for rts524A 2015-03-03T16:41:20+00:00 Micky Ching micky_ching@realsil.com.cn 2015-02-25T05:50:14+00:00 663c425f2c8d87a433629f09c5afd0af7e7e550c add support for new chip rts524A. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
add support for new chip rts524A.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: rtsx: Remove LCTLR defination 2015-03-03T16:41:19+00:00 Micky Ching micky_ching@realsil.com.cn 2015-02-25T05:50:13+00:00 19f3bd548f2750a8a7e4e6d2f25fdc5f8e2c3ee9 To enable/disable ASPM we should find LINK CONTROL register in PCI config space. All old chip use 0x80 address, but new chip may use another address, so we using pci_find_capability() to get LINK CONTROL address. rtsx_gops.c was removed, we consider to put some common operations to this file, but the actual thing is, only a group of chips are in common ops1, and another group of chips in common ops2, it is hard to decide put which ops into generic ops file. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
To enable/disable ASPM we should find LINK CONTROL register
in PCI config space. All old chip use 0x80 address, but new
chip may use another address, so we using pci_find_capability()
to get LINK CONTROL address.

rtsx_gops.c was removed, we consider to put some common operations
to this file, but the actual thing is, only a group of chips
are in common ops1, and another group of chips in common ops2,
it is hard to decide put which ops into generic ops file.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: rtsx: Update phy register 2015-03-03T16:41:19+00:00 Micky Ching micky_ching@realsil.com.cn 2015-02-25T05:50:12+00:00 b038538104d5b033d3beaffba6d6efe01246930b Update some phy register name and value for rts5249, the updated value makes chip more stable on some platform. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
Update some phy register name and value for rts5249,
the updated value makes chip more stable on some platform.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: rtsx: Update driving settings 2015-03-03T16:41:18+00:00 Micky Ching micky_ching@realsil.com.cn 2015-02-25T05:50:11+00:00 e89f231826a773ea37dfa99ab619f3ee34c06522 update card drive settings, This setting can be used for rts5249 rts524A and rts525A. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
update card drive settings, This setting can be used for rts5249
rts524A and rts525A.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: rtsx: Update PETXCFG address 2015-03-03T16:41:17+00:00 Micky Ching micky_ching@realsil.com.cn 2015-02-25T05:50:10+00:00 9e33ce79f828eb5a1bb9dd4830c7fa719d4279dc PETXCFG is defined at 0xFF03, the old 0xFE49 not used any more. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
PETXCFG is defined at 0xFF03, the old 0xFE49 not used any more.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: rtsx: Fix PM suspend for 5227 & 5249 2014-11-25T16:18:48+00:00 Micky Ching micky_ching@realsil.com.cn 2014-10-10T05:58:44+00:00 5cb5d9616a47d5383a85379afa4429382ef46b38 Fix rts5227&5249 failed send buffer cmd after suspend, PM_CTRL3 should reset before send any buffer cmd after suspend. Otherwise, buffer cmd will failed, this will lead resume fail. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
Fix rts5227&5249 failed send buffer cmd after suspend,
PM_CTRL3 should reset before send any buffer cmd after suspend.
Otherwise, buffer cmd will failed, this will lead resume fail.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: rtsx: Modify rts5249_optimize_phy 2013-10-23T15:20:59+00:00 Wei WANG wei_wang@realsil.com.cn 2013-09-13T09:45:43+00:00 26b818511c6562ce372566c219a2ef1afea35fe6 In some platforms, specially Thinkpad series, rts5249 won't be initialized properly. So we need adjust some phy parameters to improve the compatibility issue. It is a little different between simulation and real chip. We have no idea about which configuration is better before tape-out. We set default settings according to simulation, but need to tune these parameters after getting the real chip. I can't explain every change in detail here. The below information is just a rough description: PHY_REG_REV: Disable internal clkreq_tx, enable rx_pwst PHY_BPCR: No change, just turn the magic number to macro definitions PHY_PCR: Change OOBS sensitivity, from 60mV to 90mV PHY_RCR2: Control charge-pump current automatically PHY_FLD4: Use TX cmu reference clock PHY_RDR: Change RXDSEL from 30nF to 1.9nF PHY_RCR1: Change the duration between adp_st and asserting cp_en from 0.32 us to 0.64us PHY_FLD3: Adjust internal timers PHY_TUNE: Fine tune the regulator12 output voltage Signed-off-by: Wei WANG <wei_wang@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org> 
In some platforms, specially Thinkpad series, rts5249 won't be
initialized properly. So we need adjust some phy parameters to
improve the compatibility issue.

It is a little different between simulation and real chip. We have
no idea about which configuration is better before tape-out. We set
default settings according to simulation, but need to tune these
parameters after getting the real chip.

I can't explain every change in detail here. The below information is
just a rough description:

PHY_REG_REV: Disable internal clkreq_tx, enable rx_pwst
PHY_BPCR: No change, just turn the magic number to macro definitions
PHY_PCR: Change OOBS sensitivity, from 60mV to 90mV
PHY_RCR2: Control charge-pump current automatically
PHY_FLD4: Use TX cmu reference clock
PHY_RDR: Change RXDSEL from 30nF to 1.9nF
PHY_RCR1: Change the duration between adp_st and asserting cp_en from
0.32 us to 0.64us
PHY_FLD3: Adjust internal timers
PHY_TUNE: Fine tune the regulator12 output voltage

Signed-off-by: Wei WANG <wei_wang@realsil.com.cn>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
mfd: mmc: rtsx: Change default tx phase 2013-08-30T12:24:07+00:00 Wei WANG wei_wang@realsil.com.cn 2013-08-21T01:46:25+00:00 84d72f9cc21d6e41c620dd34b8248734cd02d995 The default phase can meet most cards' requirement, but it is not the optimal one. In some extreme situation, the rx phase point produced by the following tuning process will drift quite a distance. Before tuning UHS card, this patch will set a more proper initial tx phase point, which is calculated from statistic data, and can achieve a much better tx signal quality. Signed-off-by: Wei WANG <wei_wang@realsil.com.cn> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Chris Ball <cjb@laptop.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com> 
The default phase can meet most cards' requirement, but it is not the
optimal one. In some extreme situation, the rx phase point produced by
the following tuning process will drift quite a distance.
Before tuning UHS card, this patch will set a more proper initial tx
phase point, which is calculated from statistic data, and can achieve
a much better tx signal quality.

Signed-off-by: Wei WANG <wei_wang@realsil.com.cn>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>