linux-toradex.git/drivers/misc/cardreader/rts5261.c, branch v5.10-rc3 Linux kernel for Apalis and Colibri modules misc: rtsx: Use standard PCI definitions 2020-07-22T11:39:31+00:00 Bjorn Helgaas bhelgaas@google.com 2020-07-21T21:23:36+00:00 7a4462a96777b64b22412f782de226c90290bf75 When reading registers defined by the PCIe spec, use the names already defined by the PCI core. This makes maintenance of the PCI core and drivers easier. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200721212336.1159079-6-helgaas@kernel.org [ additional replacements due to changes in my tree - gregkh ] Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
When reading registers defined by the PCIe spec, use the names already
defined by the PCI core.  This makes maintenance of the PCI core and
drivers easier.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200721212336.1159079-6-helgaas@kernel.org
[ additional replacements due to changes in my tree - gregkh ]
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
misc: rtsx: Find L1 PM Substates capability instead of hard-coding 2020-07-22T11:34:27+00:00 Bjorn Helgaas bhelgaas@google.com 2020-07-21T21:23:35+00:00 ed86a9877d05b99088a409a7603828b818a433dc Instead of hard-coding the location of the L1 PM Substates capability based on the Device ID, search for it in the extended capabilities list. This works for any device, as long as it implements the L1 PM Substates capability correctly, so it doesn't require maintenance as new devices are added. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200721212336.1159079-5-helgaas@kernel.org [ minor addition due to differences in my tree - gregkh] Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
Instead of hard-coding the location of the L1 PM Substates capability based
on the Device ID, search for it in the extended capabilities list.  This
works for any device, as long as it implements the L1 PM Substates
capability correctly, so it doesn't require maintenance as new devices are
added.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200721212336.1159079-5-helgaas@kernel.org
[ minor addition due to differences in my tree - gregkh]
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
misc: rtsx: Remove rtsx_pci_read/write_config() wrappers 2020-07-22T11:29:44+00:00 Bjorn Helgaas bhelgaas@google.com 2020-07-21T21:23:34+00:00 22bf3251d7b7da0339f41ec27f2c3d4e0ec02255 rtsx_pci_read_config_dword() and similar wrappers around the PCI config accessors add very little value, and they obscure the fact that often we are accessing standard PCI registers that should be coordinated with the PCI core. Remove the wrappers and use the PCI config accessors directly. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200721212336.1159079-4-helgaas@kernel.org [ fixed up some other instances as original patch was based on old tree - gregkh Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
rtsx_pci_read_config_dword() and similar wrappers around the PCI config
accessors add very little value, and they obscure the fact that often we
are accessing standard PCI registers that should be coordinated with the
PCI core.

Remove the wrappers and use the PCI config accessors directly.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200721212336.1159079-4-helgaas@kernel.org
[ fixed up some other instances as original patch was based on old tree - gregkh
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
misc: rtsx: Use pcie_capability_clear_and_set_word() for PCI_EXP_LNKCTL 2020-05-22T07:38:13+00:00 Bjorn Helgaas bhelgaas@google.com 2020-05-21T18:05:43+00:00 3d1e7aa80d1c0e7ce8313f21c1e9c14a12d3ba48 Instead of using the driver-specific rtsx_pci_update_cfg_byte() to update the PCIe Link Control Register, use pcie_capability_clear_and_set_word() like the rest of the kernel does. This makes it easier to maintain ASPM across the PCI core and drivers. Remove the now-unused rtsx_pci_update_cfg_byte() and ASPM_MASK_NEG definitions. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20200521180545.1159896-5-helgaas@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
Instead of using the driver-specific rtsx_pci_update_cfg_byte() to update
the PCIe Link Control Register, use pcie_capability_clear_and_set_word()
like the rest of the kernel does.  This makes it easier to maintain ASPM
across the PCI core and drivers.

Remove the now-unused rtsx_pci_update_cfg_byte() and ASPM_MASK_NEG
definitions.

No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20200521180545.1159896-5-helgaas@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
misc: rtsx: Removed unused dev_aspm_mode 2020-05-22T07:38:12+00:00 Bjorn Helgaas bhelgaas@google.com 2020-05-21T18:05:41+00:00 51876e22bf7f8f5d2b9ca7d2b3dcbfaaac2991a9 The struct rtsx_cr_option.dev_aspm_mode member is never set to anything other than DEV_ASPM_DYNAMIC (0). Remove it and code that tests it. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20200521180545.1159896-3-helgaas@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
The struct rtsx_cr_option.dev_aspm_mode member is never set to anything
other than DEV_ASPM_DYNAMIC (0).  Remove it and code that tests it.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20200521180545.1159896-3-helgaas@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
misc: rtsx: Improve compatibility for rts5261 2020-04-23T14:55:24+00:00 Rui Feng rui_feng@realsil.com.cn 2020-04-15T02:37:17+00:00 c18c1f103503981bfbb3b9c3cdf3d2ea14f8e010 Change initial clock to improve compatibility for rts5261 Signed-off-by: Rui Feng <rui_feng@realsil.com.cn> Link: https://lore.kernel.org/r/1586918237-3016-1-git-send-email-rui_feng@realsil.com.cn Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
Change initial clock to improve compatibility for rts5261

Signed-off-by: Rui Feng <rui_feng@realsil.com.cn>
Link: https://lore.kernel.org/r/1586918237-3016-1-git-send-email-rui_feng@realsil.com.cn
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
mmc: rtsx_pci: Fix support for speed-modes that relies on tuning 2020-03-18T10:55:02+00:00 Ricky Wu ricky_wu@realtek.com 2020-03-16T02:52:32+00:00 4686392c32361c97e8434adf9cc77ad7991bfa81 The TX/RX register should not be treated the same way to allow for better support of tuning. Fix this by using a default initial value for TX. Signed-off-by: Ricky Wu <ricky_wu@realtek.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200316025232.1167-1-ricky_wu@realtek.com [Ulf: Updated changelog] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
The TX/RX register should not be treated the same way to allow for better
support of tuning. Fix this by using a default initial value for TX.

Signed-off-by: Ricky Wu <ricky_wu@realtek.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200316025232.1167-1-ricky_wu@realtek.com
[Ulf: Updated changelog]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
misc: rtsx: Fix impossible condition 2020-01-14T14:06:07+00:00 Rui Feng rui_feng@realsil.com.cn 2019-11-20T01:40:06+00:00 4d6168314d4c504c240087ac22d1acc01dad3299 A u8 can only go up to 255, condition n > 396 is impossible, so change u8 to u16. Signed-off-by: Rui Feng <rui_feng@realsil.com.cn> Link: https://lore.kernel.org/r/1574214006-13540-1-git-send-email-rui_feng@realsil.com.cn Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
A u8 can only go up to 255, condition n > 396 is
impossible, so change u8 to u16.

Signed-off-by: Rui Feng <rui_feng@realsil.com.cn>
Link: https://lore.kernel.org/r/1574214006-13540-1-git-send-email-rui_feng@realsil.com.cn
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
misc: rtsx: Add support for RTS5261 2019-11-14T05:07:48+00:00 Rui Feng rui_feng@realsil.com.cn 2019-10-21T08:05:05+00:00 c0e5f4e73a7148e18b763067d181661987cb4c09 Add support for new chip rts5261. In order to support rts5261, the definitions of some internal registers and workflow have to be modified and are different from its predecessors. So we need this patch to ensure RTS5261 can work. Signed-off-by: Rui Feng <rui_feng@realsil.com.cn> Link: https://lore.kernel.org/r/1571645105-5028-1-git-send-email-rui_feng@realsil.com.cn Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
Add support for new chip rts5261.
In order to support rts5261, the definitions of some internal registers
and workflow have to be modified and are different from its predecessors.
So we need this patch to ensure RTS5261 can work.

Signed-off-by: Rui Feng <rui_feng@realsil.com.cn>
Link: https://lore.kernel.org/r/1571645105-5028-1-git-send-email-rui_feng@realsil.com.cn
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>