Switching off and switching on the power rails during
suspend and resume. Passing the power rail name, maxV
and minV through platform data.

Bug 793796

Change-Id: I6c80c1a23c9681043d11ffdd210dc6d2146bdd2e
Reviewed-on: http://git-master/r/29660
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Make SD card write protection GPIO optional.
Some boards such as Whistler do not support this GPIO.
Default behaviour for this case is write-enabled.

Bug 686892.

Change-Id: I5e16e2260e681145e52d604abcfa38135e2be873
Original-Change-Id: If5253bfbadeafbffdf4f69ff0315fcf572886e0e
Reviewed-in: http://git-master/r/#change,21101
Reviewed-on: http://git-master/r/27542
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Change-Id: I5e16e2260e681145e52d604abcfa38135e2be873

this work around is no more required as proper fix is
done in bcm driver.

Bug 795460

Original-Change-Id: I3ad30c1211ae5492307d32e9788a8db977a54d94
Reviewed-on: http://git-master/r/26687
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Rahul Bansal <rbansal@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: Ia17ac97478bf3b750c9122991543c0237a31c0ac

Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a

Enabling SDHCI_POWER_ON bit during SDIO resume. Without
this bit, SDIO card clock is not enabled and SDIO resume
fails.

Bug 802383

Original-Change-Id: I6d897c542ba2be625720804e0d04d81f0ce0cedb
Reviewed-on: http://git-master/r/23211
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Change-Id: I0b01fe847fa2f8e470775dd443e26a6a1895a0e5

Enabling controller clock before MMC_POWER_UP to ensure
proper register read/writes. Currently, during initialization
SDHCI_POWER_ON is being set without controller clock enabled.

Original-Change-Id: Ifc7b9f14eaf1ad5641d6edabaae4eca050c0ac6f
Reviewed-on: http://git-master/r/23186
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Change-Id: I31b2d2a3075646e6b6605ad7c55dda3d621ebc7d

Properly enabling/disabling all sdmmc clocks to ensure the
clock refcount is correctly maintained.
Clocks are disabled in suspend and set in resume.

Bug 793796

Original-Change-Id: I941b979e16c347df46761cd21a986fa7768ed705
Reviewed-on: http://git-master/r/23185
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Change-Id: I14c57c175291d6bce2dd08df0d54d984f073d568

Fix build break on ventana due to improper use
of kernel config paramters.

Original-Change-Id: If6f54e1f305e960f8bf935058f48b0e77adce6c6
Reviewed-on: http://git-master/r/22639
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Ia78069e7c3413e031dcb2df61216bfb577a693b5

Unsetting bus speed mode variable after reset to
ensure that the uhs mode is set properly.

Original-Change-Id: I098a0df1289acefe01c391da622132a3562382fe
Reviewed-on: http://git-master/r/22423
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Change-Id: I0ffd0ab93b7fb72e2a7ae8d060b264d4f735df03

Set SDHCI_QUIRK_8_BIT_DATA if the platform supports 8-bit
data. If not, use 4-bit data width.

Bug 794550
Bug 796574
Bug 796220

Original-Change-Id: Icd8536e0e0b2db77d1443fbbf0ba6b90b51b62ca
Reviewed-on: http://git-master/r/20746
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I85a1f68f2faf0751ada631132b19116e3b574bc5