linux-toradex.git/drivers/mtd/spi-nor/controllers, branch v6.18 Linux kernel for Apalis and Colibri modules mtd: Switch back to struct platform_driver::remove() 2024-10-21T09:58:07+00:00 Uwe Kleine-König u.kleine-koenig@baylibre.com 2024-10-07T20:58:07+00:00 f8470006c4d6bd54dbf9a3479f85e13387bff56d After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/mtd to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20241007205803.444994-10-u.kleine-koenig@baylibre.com 
After commit 0edb555a65d1 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.

Convert all platform drivers below drivers/mtd to use .remove(), with
the eventual goal to drop struct platform_driver::remove_new(). As
.remove() and .remove_new() have the same prototypes, conversion is done
by just changing the structure member name in the driver initializer.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20241007205803.444994-10-u.kleine-koenig@baylibre.com
mtd: spi-nor: nxp-spifi: Convert to platform remove callback returning void 2023-10-16T08:56:48+00:00 Uwe Kleine-König u.kleine-koenig@pengutronix.de 2023-10-08T20:01:43+00:00 3ee355dbc78d3dcb7f17a8b3c8eaaa38c54499b7 The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/linux-mtd/20231008200143.196369-21-u.kleine-koenig@pengutronix.de 
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.

To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/linux-mtd/20231008200143.196369-21-u.kleine-koenig@pengutronix.de
mtd: spi-nor: hisi-sfc: Convert to platform remove callback returning void 2023-10-16T08:56:48+00:00 Uwe Kleine-König u.kleine-koenig@pengutronix.de 2023-10-08T20:01:42+00:00 ac2bc659822e844d21361623c5964c5cddd01c60 The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/linux-mtd/20231008200143.196369-20-u.kleine-koenig@pengutronix.de 
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.

To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/linux-mtd/20231008200143.196369-20-u.kleine-koenig@pengutronix.de
Merge tag 'spi-nor/for-6.6' into mtd/next 2023-08-18T14:40:02+00:00 Miquel Raynal miquel.raynal@bootlin.com 2023-08-18T14:39:53+00:00 f7091fb725dcabc171c5fba28a6ce38beb08f205 SPI NOR core changes: * fix assumption on enabling quad mode in spi_nor_write_16bit_sr_and_check() * avoid setting SRWD bit in SR if WP# signal not connected as it will configure the SR permanently as read only. Add "no-wp" dt property. * clarify the need for spi-nor compatibles in dt-bindings SPI NOR manufacturer drivers changes: * spansion: - add support for S28HS02GT - switch methods to use vreg_offset from SFDP instead of hardcoding the register value * microchip/sst: - add support for sst26vf032b flash * winbond: - correct flags for Winbond w25q128 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> 
SPI NOR core changes:
* fix assumption on enabling quad mode in
  spi_nor_write_16bit_sr_and_check()
* avoid setting SRWD bit in SR if WP# signal not connected as it will
  configure the SR permanently as read only. Add "no-wp" dt property.
* clarify the need for spi-nor compatibles in dt-bindings

SPI NOR manufacturer drivers changes:
* spansion:
  - add support for S28HS02GT
  - switch methods to use vreg_offset from SFDP instead of hardcoding
    the register value
* microchip/sst:
  - add support for sst26vf032b flash
* winbond:
  - correct flags for Winbond w25q128

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
mtd: spi-nor: nxp-spifi: Use helper function devm_clk_get_enabled() 2023-08-18T10:14:56+00:00 Li Zetao lizetao1@huawei.com 2023-08-18T07:46:41+00:00 69d50d0461a182872b7f7892702fa3a1ba95950d Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enable (and possibly prepare) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clock explicitly, so drop the label "dis_clks" and "dis_clk_reg". Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Li Zetao <lizetao1@huawei.com> Link: https://lore.kernel.org/r/20230818074642.308166-12-lizetao1@huawei.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> 
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enable (and possibly
prepare) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clock explicitly, so drop
the label "dis_clks" and "dis_clk_reg".

Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Li Zetao <lizetao1@huawei.com>
Link: https://lore.kernel.org/r/20230818074642.308166-12-lizetao1@huawei.com
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
mtd: Explicitly include correct DT includes 2023-07-27T15:03:41+00:00 Rob Herring robh@kernel.org 2023-07-14T17:47:49+00:00 c2fc6b6947905eee832e9ef445df4803f0056cc6 The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230714174751.4060439-1-robh@kernel.org 
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it was merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230714174751.4060439-1-robh@kernel.org
mtd: Use of_property_read_bool() for boolean properties 2023-03-22T16:02:17+00:00 Rob Herring robh@kernel.org 2023-03-10T14:47:15+00:00 57150c40b6391bc350c6016641b2a487a3de3cba It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to to of_property_read_bool(). Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230310144716.1543995-1-robh@kernel.org 
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_property/of_find_property functions for reading properties.
Convert reading boolean properties to to of_property_read_bool().

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230310144716.1543995-1-robh@kernel.org
mtd: spi-nor: s/addr_width/addr_nbytes 2022-07-28T02:11:56+00:00 Tudor Ambarus tudor.ambarus@microchip.com 2022-07-25T09:24:59+00:00 c452d49849d48bd37ae97fc2bc92c6435707c35f Address width was an unfortunate name, as it means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. s/addr_width/addr_nbytes throughout the entire SPI NOR framework. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-2-tudor.ambarus@microchip.com 
Address width was an unfortunate name, as it means the number of IO lines
used for the address, whereas in the code it is used as the number of
address bytes. s/addr_width/addr_nbytes throughout the entire SPI NOR
framework.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220725092505.446315-2-tudor.ambarus@microchip.com
spi: spi-mem: Convert Aspeed SMC driver to spi-mem 2022-05-16T11:59:15+00:00 Cédric Le Goater clg@kaod.org 2022-05-09T17:56:08+00:00 e3228ed92893458e360ba2be8d75d859e115e552 This SPI driver adds support for the Aspeed static memory controllers of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface. * AST2600 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . Only supports SPI type flash memory . different segment register interface . single, dual and quad mode. * AST2600 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . different segment register interface . single, dual and quad mode. * AST2500 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver . single, dual mode. * AST2500 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . single, dual mode. * AST2400 New Static Memory Controller (also referred as FMC) . BMC firmware . New register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. . single, dual and quad mode. Each controller has a memory range on which flash devices contents are mapped. Each device is assigned a window that can be changed at bootime with the Segment Address Registers. Each SPI flash device can then be accessed in two modes: Command and User. When in User mode, SPI transfers are initiated with accesses to the memory segment of a device. When in Command mode, memory operations on the memory segment of a device generate SPI commands automatically using a Control Register for the settings. This initial patch adds support for User mode. Command mode needs a little more work to check that the memory window on the AHB bus fits the device size. It will come later when support for direct mapping is added. Single and dual mode RX transfers are supported. Other types than SPI are not supported. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-4-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org> 
This SPI driver adds support for the Aspeed static memory controllers
of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.

 * AST2600 Firmware SPI Memory Controller (FMC)
   . BMC firmware
   . 3 chip select pins (CE0 ~ CE2)
   . Only supports SPI type flash memory
   . different segment register interface
   . single, dual and quad mode.

 * AST2600 SPI Flash Controller (SPI1 and SPI2)
   . host firmware
   . 2 chip select pins (CE0 ~ CE1)
   . different segment register interface
   . single, dual and quad mode.

 * AST2500 Firmware SPI Memory Controller (FMC)
   . BMC firmware
   . 3 chip select pins (CE0 ~ CE2)
   . supports SPI type flash memory (CE0-CE1)
   . CE2 can be of NOR type flash but this is not supported by the driver
   . single, dual mode.

 * AST2500 SPI Flash Controller (SPI1 and SPI2)
   . host firmware
   . 2 chip select pins (CE0 ~ CE1)
   . single, dual mode.

 * AST2400 New Static Memory Controller (also referred as FMC)
   . BMC firmware
   . New register set
   . 5 chip select pins (CE0 ∼ CE4)
   . supports NOR flash, NAND flash and SPI flash memory.
   . single, dual and quad mode.

Each controller has a memory range on which flash devices contents are
mapped. Each device is assigned a window that can be changed at bootime
with the Segment Address Registers.

Each SPI flash device can then be accessed in two modes: Command and
User. When in User mode, SPI transfers are initiated with accesses to
the memory segment of a device. When in Command mode, memory
operations on the memory segment of a device generate SPI commands
automatically using a Control Register for the settings.

This initial patch adds support for User mode. Command mode needs a little
more work to check that the memory window on the AHB bus fits the device
size. It will come later when support for direct mapping is added.

Single and dual mode RX transfers are supported. Other types than SPI
are not supported.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Tested-by: Tao Ren <rentao.bupt@gmail.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220509175616.1089346-4-clg@kaod.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 2022-03-25T20:35:34+00:00 Linus Torvalds torvalds@linux-foundation.org 2022-03-25T20:35:34+00:00 e35a4a4e13c35f500a8d38e836b5e335c7515494 Pull MTD updates from Miquel Raynal: "There has been a lot of activity in the MTD subsystem recently, with a number of SPI-NOR cleanups as well as the introduction of ECC engines that can be used by SPI controllers (hence a few SPI patches in here). Core MTD changes: - Replace the expert mode symbols with a single helper - Fix misuses of of_match_ptr() - Remove partid and partname debugfs files - tests: Fix eraseblock read speed miscalculation for lower partition sizes - TRX parser: Allow to use on MediaTek MIPS SoCs MTD driver changes: - spear_smi: use GFP_KERNEL - mchp48l640: Add SPI ID table - mchp23k256: Add SPI ID table - blkdevs: Avoid soft lockups with some mtd/spi devices - aspeed-smc: Improve probe resilience Hyperbus changes: - HBMC_AM654 should depend on ARCH_K3 NAND core changes: - ECC: - Add infrastructure to support hardware engines - Add a new helper to retrieve the ECC context - Provide a helper to retrieve a pilelined engine device NAND-ECC changes: - Macronix ECC engine: - Add Macronix external ECC engine support - Support SPI pipelined mode - Make two read-only arrays static const - Fix compile test issue Raw NAND core changes: - Fix misuses of of_match_node() - Rework of_get_nand_bus_width() - Remove of_get_nand_on_flash_bbt() wrapper - Protect access to rawnand devices while in suspend - bindings: Document the wp-gpios property Rax NAND controller driver changes: - atmel: Fix refcount issue in atmel_nand_controller_init - nandsim: - Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern - Merge repeat codes in ns_switch_state - Replace overflow check with kzalloc to single kcalloc - rockchip: Fix platform_get_irq.cocci warning - stm32_fmc2: Add NAND Write Protect support - pl353: Set the nand chip node as the flash node - brcmnand: Fix sparse warnings in bcma_nand - omap_elm: Remove redundant variable 'errors' - gpmi: - Support fast edo timings for mx28 - Validate controller clock rate - Fix controller timings setting - brcmnand: - Add BCMA shim - BCMA controller uses command shift of 0 - Allow platform data instantation - Add platform data structure for BCMA - Allow working without interrupts - Move OF operations out of brcmnand_init_cs() - Avoid pdev in brcmnand_init_cs() - Allow SoC to provide I/O operations - Assign soc as early as possible Onenand changes: - Check for error irq SPI-NAND core changes: - Delay a little bit the dirmap creation - Create direct mapping descriptors for ECC operations SPI-NAND driver changes: - macronix: Use random program load SPI NOR core changes: - Move vendor specific code out of the core into vendor drivers. - Unify all function and object names in the vendor modules. - Make setup() callback optional to improve readability. - Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash declaration. SPI changes: - Macronix SPI controller: - Fix the transmit path - Create a helper to configure the controller before an operation - Create a helper to ease the start of an operation - Add support for direct mapping - Add support for pipelined ECC operations - spi-mem: - Introduce a capability structure - Check the controller extra capabilities - cadence-quadspi/mxic: Provide capability structures - Kill the spi_mem_dtr_supports_op() helper - Add an ecc parameter to the spi_mem_op structure Binding changes: - Dropped mtd/cortina,gemini-flash.txt - Convert BCM47xx partitions to json-schema - Vendor prefixes: Clarify Macronix prefix - SPI NAND: Convert spi-nand description file to yaml - Raw NAND chip: Create a NAND chip description - Raw NAND controller: - Harmonize the property types - Fix a comment in the examples - Fix the reg property description - Describe Macronix NAND ECC engine - Macronix SPI controller: - Document the nand-ecc-engine property - Convert to yaml - The interrupt property is not mandatory" * tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits) mtd: nand: ecc: mxic: Fix compile test issue mtd: nand: mxic-ecc: make two read-only arrays static const mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3 mtd: core: Remove partid and partname debugfs files dt-bindings: mtd: partitions: convert BCM47xx to the json-schema mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init mtd: rawnand: rockchip: fix platform_get_irq.cocci warning mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set mtd: spi-nor: renumber flags mtd: spi-nor: slightly change code style in spi_nor_sr_ready() mtd: spi-nor: spansion: rename vendor specific functions and defines mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag mtd: spi-nor: move all spansion specifics into spansion.c mtd: spi-nor: spansion: slightly rework control flow in late_init() mtd: spi-nor: micron-st: rename vendor specific functions and defines mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag mtd: spi-nor: move all micron-st specifics into micron-st.c mtd: spi-nor: xilinx: correct the debug message mtd: spi-nor: xilinx: rename vendor specific functions and defines ... 
Pull MTD updates from Miquel Raynal:
 "There has been a lot of activity in the MTD subsystem recently, with a
  number of SPI-NOR cleanups as well as the introduction of ECC engines
  that can be used by SPI controllers (hence a few SPI patches in here).

  Core MTD changes:
   - Replace the expert mode symbols with a single helper
   - Fix misuses of of_match_ptr()
   - Remove partid and partname debugfs files
   - tests: Fix eraseblock read speed miscalculation for lower partition
     sizes
   - TRX parser: Allow to use on MediaTek MIPS SoCs

  MTD driver changes:
   - spear_smi: use GFP_KERNEL
   - mchp48l640: Add SPI ID table
   - mchp23k256: Add SPI ID table
   - blkdevs: Avoid soft lockups with some mtd/spi devices
   - aspeed-smc: Improve probe resilience

  Hyperbus changes:
   - HBMC_AM654 should depend on ARCH_K3

  NAND core changes:
   - ECC:
      - Add infrastructure to support hardware engines
      - Add a new helper to retrieve the ECC context
      - Provide a helper to retrieve a pilelined engine device

  NAND-ECC changes:
   - Macronix ECC engine:
      - Add Macronix external ECC engine support
      - Support SPI pipelined mode
      - Make two read-only arrays static const
      - Fix compile test issue

  Raw NAND core changes:
   - Fix misuses of of_match_node()
   - Rework of_get_nand_bus_width()
   - Remove of_get_nand_on_flash_bbt() wrapper
   - Protect access to rawnand devices while in suspend
   - bindings: Document the wp-gpios property

  Rax NAND controller driver changes:
   - atmel: Fix refcount issue in atmel_nand_controller_init
   - nandsim:
      - Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern
      - Merge repeat codes in ns_switch_state
      - Replace overflow check with kzalloc to single kcalloc
   - rockchip: Fix platform_get_irq.cocci warning
   - stm32_fmc2: Add NAND Write Protect support
   - pl353: Set the nand chip node as the flash node
   - brcmnand: Fix sparse warnings in bcma_nand
   - omap_elm: Remove redundant variable 'errors'
   - gpmi:
      - Support fast edo timings for mx28
      - Validate controller clock rate
      - Fix controller timings setting
   - brcmnand:
      - Add BCMA shim
      - BCMA controller uses command shift of 0
      - Allow platform data instantation
      - Add platform data structure for BCMA
      - Allow working without interrupts
      - Move OF operations out of brcmnand_init_cs()
      - Avoid pdev in brcmnand_init_cs()
      - Allow SoC to provide I/O operations
      - Assign soc as early as possible

  Onenand changes:
   - Check for error irq

  SPI-NAND core changes:
   - Delay a little bit the dirmap creation
   - Create direct mapping descriptors for ECC operations

  SPI-NAND driver changes:
   - macronix: Use random program load

  SPI NOR core changes:
   - Move vendor specific code out of the core into vendor drivers.
   - Unify all function and object names in the vendor modules.
   - Make setup() callback optional to improve readability.
   - Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash
     declaration.

  SPI changes:
   - Macronix SPI controller:
      - Fix the transmit path
      - Create a helper to configure the controller before an operation
      - Create a helper to ease the start of an operation
      - Add support for direct mapping
      - Add support for pipelined ECC operations
   - spi-mem:
      - Introduce a capability structure
      - Check the controller extra capabilities
      - cadence-quadspi/mxic: Provide capability structures
      - Kill the spi_mem_dtr_supports_op() helper
      - Add an ecc parameter to the spi_mem_op structure

  Binding changes:
   - Dropped mtd/cortina,gemini-flash.txt
   - Convert BCM47xx partitions to json-schema
   - Vendor prefixes: Clarify Macronix prefix
   - SPI NAND: Convert spi-nand description file to yaml
   - Raw NAND chip: Create a NAND chip description
   - Raw NAND controller:
      - Harmonize the property types
      - Fix a comment in the examples
      - Fix the reg property description
   - Describe Macronix NAND ECC engine
   - Macronix SPI controller:
      - Document the nand-ecc-engine property
      - Convert to yaml
      - The interrupt property is not mandatory"

* tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits)
  mtd: nand: ecc: mxic: Fix compile test issue
  mtd: nand: mxic-ecc: make two read-only arrays static const
  mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3
  mtd: core: Remove partid and partname debugfs files
  dt-bindings: mtd: partitions: convert BCM47xx to the json-schema
  mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes
  mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init
  mtd: rawnand: rockchip: fix platform_get_irq.cocci warning
  mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set
  mtd: spi-nor: renumber flags
  mtd: spi-nor: slightly change code style in spi_nor_sr_ready()
  mtd: spi-nor: spansion: rename vendor specific functions and defines
  mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag
  mtd: spi-nor: move all spansion specifics into spansion.c
  mtd: spi-nor: spansion: slightly rework control flow in late_init()
  mtd: spi-nor: micron-st: rename vendor specific functions and defines
  mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag
  mtd: spi-nor: move all micron-st specifics into micron-st.c
  mtd: spi-nor: xilinx: correct the debug message
  mtd: spi-nor: xilinx: rename vendor specific functions and defines
  ...