linux-toradex.git/drivers/mtd/spi-nor, branch v6.3-rc5

mtd: spi-nor: fix memory leak when using debugfs_lookup()

2023-03-06T06:52:03+00:00

When calling debugfs_lookup() the result must have dput() called on it,
otherwise the memory will leak over time.  To solve this, remove the
lookup and create the directory on the first device found, and then
remove it when the module is unloaded.

Cc: Tudor Ambarus 
Cc: Pratyush Yadav 
Cc: Miquel Raynal 
Cc: Richard Weinberger 
Cc: Vignesh Raghavendra 
Cc: linux-mtd@lists.infradead.org
Reviewed-by: Michael Walle 
Link: https://lore.kernel.org/r/20230208160230.2179905-1-gregkh@linuxfoundation.org
Signed-off-by: Greg Kroah-Hartman

mtd: spi-nor: Sort headers alphabetically

2023-02-06T08:37:03+00:00

Sort headers alphabetically - it helps locating duplicates, and makes it
easier to figure out where to insert new headers. Alphabetic order should
also prove that each header is self-contained, i.e. can be included without
prerequisites.

Link: https://lore.kernel.org/r/20230202144628.14443-1-tudor.ambarus@linaro.org
Signed-off-by: Tudor Ambarus

mtd: spi-nor: Fix shift-out-of-bounds in spi_nor_set_erase_type

2023-02-06T08:36:18+00:00

spi_nor_set_erase_type() was used either to set or to mask out an erase
type. When we used it to mask out an erase type a shift-out-of-bounds
was hit:
UBSAN: shift-out-of-bounds in drivers/mtd/spi-nor/core.c:2237:24
shift exponent 4294967295 is too large for 32-bit type 'int'

The setting of the size_{shift, mask} and of the opcode are unnecessary
when the erase size is zero, as throughout the code just the erase size
is considered to determine whether an erase type is supported or not.
Setting the opcode to 0xFF was wrong too as nobody guarantees that 0xFF
is an unused opcode. Thus when masking out an erase type, just set the
erase size to zero. This will fix the shift-out-of-bounds.

Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories")
Cc: stable@vger.kernel.org
Reported-by: Alexander Stein 
Signed-off-by: Louis Rannou 
Tested-by: Alexander Stein 
Link: https://lore.kernel.org/r/20230203070754.50677-1-tudor.ambarus@linaro.org
[ta: refine changes, new commit message, fix compilation error]
Signed-off-by: Tudor Ambarus

mtd: spi-nor: Create macros to define chip IDs and geometries

2023-01-26T17:52:47+00:00

The INFO() macro defines an ID array and a couple of geometry
properties. Right now all its lines are duplicated twice because of the
INFO6() macro (for extended IDs) and soon as well we will need to add a
geometry parameter to include the number of banks.

In order to limit the code duplication, let's create a number of
intermediate macros which will facilitate defining high-level INFOX()
macros.

There is no functional change.

Signed-off-by: Miquel Raynal 
Reviewed-by: Pratyush Yadav 
Link: https://lore.kernel.org/r/20221215081241.407098-2-miquel.raynal@bootlin.com
Signed-off-by: Tudor Ambarus

mtd: spi-nor: spansion: Make CFRx reg fields generic

2023-01-26T17:41:59+00:00

Cypress defines two flavors of configuration registers, volatile and
non volatile, and both use the same bit fields. Rename the bitfields in
the configuration registers so that they can be used for both flavors.

Signed-off-by: Tudor Ambarus 
Reviewed-by: Dhruva Gole 
Reviewed-by: Takahiro Kuwano 
Reviewed-by: Pratyush Yadav 
Link: https://lore.kernel.org/linux-mtd/20230110164703.83413-2-tudor.ambarus@linaro.org

mtd: spi-nor: spansion: Consider reserved bits in CFR5 register

2023-01-26T17:40:31+00:00

CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS}
definition, stop using magic numbers and describe the missing bit fields
in CFR5 register. This is useful for both readability and future possible
addition of Octal STR mode support.

Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash")
Cc: stable@vger.kernel.org
Reported-by: Takahiro Kuwano 
Signed-off-by: Tudor Ambarus 
Reviewed-by: Dhruva Gole 
Reviewed-by: Pratyush Yadav 
Tested-by: Dhruva Gole 
Link: https://lore.kernel.org/linux-mtd/20230110164703.83413-1-tudor.ambarus@linaro.org

mtd: spi-nor: core: fix implicit declaration warning

2023-01-26T17:36:31+00:00

spi-nor/core.c needs to include linux/delay.h,
or it would raise below compile warning:

drivers/mtd/spi-nor/core.c: In function ‘spi_nor_soft_reset’:
drivers/mtd/spi-nor/core.c:2779:2: error: implicit declaration of function ‘usleep_range’ [-Werror=implicit-function-declaration]
 2779 |  usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);
      |  ^~~~~~~~~~~~

Fixes: d73ee7534cc5 ("mtd: spi-nor: core: perform a Soft Reset on shutdown")
Signed-off-by: Zeng Heng 
Signed-off-by: Tudor Ambarus 
Link: https://lore.kernel.org/r/20220923031457.56103-1-zengheng4@huawei.com

mtd: spi-nor: sfdp: Use SFDP_DWORD() macro for optional parameter tables

2022-12-26T07:47:04+00:00

Change 0-based indexing values of parameter tables to 1-based ones by
SFDP_DWORD() macro.

Suggested-by: Tudor Ambarus 
Signed-off-by: Takahiro Kuwano 
Signed-off-by: Tudor Ambarus 
Link: https://lore.kernel.org/r/48cb008b40fdef4bf7f87e37029efaa2bfefa9ef.1672026365.git.Takahiro.Kuwano@infineon.com

mtd: spi-nor: sfdp: Rename BFPT_DWORD() macro to SFDP_DWORD()

2022-12-26T07:47:04+00:00

BFPT_DWORD() converts 1-based indexing to 0-based indexing for C arrays,
and is used in BFPT parse. Per JESD216F.02, the conversion is applicable
to other parameter tables than BFPT. This patch renames the macro to
SFDP_DWORD() so that we can use it for other parameter tables than BFPT.

Suggested-by: Tudor Ambarus 
Signed-off-by: Takahiro Kuwano 
Signed-off-by: Tudor Ambarus 
Link: https://lore.kernel.org/r/e42feac840fe3a31187419e91b2d514d9f259d15.1672026365.git.Takahiro.Kuwano@infineon.com

mtd: spi-nor: sfdp: Fix index value for SCCR dwords

2022-12-26T07:47:01+00:00

Array index for SCCR 22th DOWRD should be 21.

Fixes: 981a8d60e01f ("mtd: spi-nor: Parse SFDP SCCR Map")
Signed-off-by: Takahiro Kuwano 
Signed-off-by: Tudor Ambarus 
Reviewed-by: Michael Walle 
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/d8a2a77c2c95cf776e7dcae6392d29fdcf5d6307.1672026365.git.Takahiro.Kuwano@infineon.com