Conflicts: arch/arm/mach-tegra/tegra3_usb_phy.c arch/arm/mach-tegra/usb_phy.c drivers/usb/gadget/tegra_udc.c drivers/usb/otg/Makefile drivers/video/tegra/fb.c sound/soc/tegra/tegra_pcm.c
Merge with latest NVIDIA L4T R16. Only real conflict concerning inverted VBUS gpio support.
Expanding NOR functionality to work with ADMUX and Burst mode for Micron Support in E1853. Bug 989919 Bug 966833 - Adding fields for picking MUX vs NONMUX and picking Async, Paging, Burst mode for reads - Added run time decision between them - 1853 specific settings for Async NOR - 1852 specific settings for NOR - 1853 NOR timings changed Reviewed-on: http://git-master/r/122286 (cherry picked from commit a242e7194c7de559d22fe5b275a8782086f10e50) Change-Id: I79de1d52d4c7199c83b380c2fa6d8cae6b35f09d Signed-off-by: Bob Johnston <BJohnston@nvidia.com> Reviewed-on: http://git-master/r/124946 Tested-by: Bob Johnston <bjohnston@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Using UBI on tegra can give messages like:
root@colibri-t20:~# ubiattach -m 0
[ 115.218710] UBI: attaching mtd0 to ubi0
[ 115.229108] UBI error: io_init: bad write buffer size 0 for 4096 min. I/O unit
ubiattach: error!: cannot attach mtd0
error 22 (Invalid argument)
The writebufsize concept was introduce by commit
"0e4ca7e mtd: add writebufsize field to mtd_info struct" and it represents
the maximum amount of data the device writes to the media at a time. This is
an important parameter for UBIFS which is used during recovery and which
basically defines how big a corruption caused by a power cut can be.
Set writebufsize to the flash page size because it is the maximum amount of
data it writes at a time.
add compilation flag to treat warnings as errors handle error of variable declaration bug 949219 Change-Id: Iac05d4d0e4c4cbf39a534b7aee32c0dac57ae49d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/118027 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com> Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
The gpio mode of pin is configured when setting direction and hence this call is no more required. Change-Id: Id1730f48d43134c67eb1e6edf70884e3e5f582d2 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/120849 Reviewed-by: Automatic_Commit_Validation_User
add compilation flag to treat warnings as errors bug 949219 Change-Id: Iac1b0e608ac5b19f5f84380ab7ffc76e14c3d7a0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/118033 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Call dma sync single api's to maintain coherency between CPU, dma and device in data transfers. bug 984029 bug 980884 Change-Id: I50b5a24a7ce482f473670347af3c75d6975c6060 Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/105917 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
timing1_read was initialized with timing0 from nor platform data changed the same to use timing1 from platform data instead of timing0 Bug 934187 Change-Id: I04c41323de25fb2bb53dac91301cee9c0820707a Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/95293 Reviewed-on: http://git-master/r/100904 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Amlan Kundu <akundu@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>