linux-toradex.git/drivers/net/ethernet/tehuti, branch master

net: Fix typos

2025-07-25T17:29:07+00:00

Fix typos in comments and error messages.

Signed-off-by: Bjorn Helgaas 
Reviewed-by: David Arinzon 
Reviewed-by: Simon Horman 
Link: https://patch.msgid.link/20250723201528.2908218-1-helgaas@kernel.org
Signed-off-by: Jakub Kicinski

net: tn40xx: add pci-id of the aqr105-based Tehuti TN4010 cards

2025-03-25T20:53:21+00:00

Add the PCI-ID of the AQR105-based Tehuti TN4010 cards to allow loading
of the tn40xx driver on these cards. Here, I chose the detailed definition
with the subvendor ID similar to the QT2025 cards with the PCI-ID
TEHUTI:0x4022, because there is a card with an AQ2104 hiding amongst the
AQR105 cards, and they all come with the same PCI-ID (TEHUTI:0x4025). But
the AQ2104 is currently not supported.

Signed-off-by: Hans-Frieder Vogt 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20250322-tn9510-v3a-v7-7-672a9a3d8628@gmx.net
Signed-off-by: Jakub Kicinski

net: tn40xx: prepare tn40xx driver to find phy of the TN9510 card

2025-03-25T20:53:21+00:00

Prepare the tn40xx driver to load for Tehuti TN9510 cards, which require
bit 3 in the register TN40_REG_MDIO_CMD_STAT to be set. The function of bit
3 is unclear, but may have something to do with the length of the preamble
in the MDIO communication. If bit 3 is not set, the PHY will not be found
when performing a scan for PHYs. Use the available tn40_mdio_set_speed
function which includes setting bit 3. Just move the function to before the
devm_mdio_register function, which scans the mdio bus for PHYs.

Signed-off-by: Hans-Frieder Vogt 
Reviewed-by: Andrew Lunn 
Reviewed-by: FUJITA Tomonori 
Link: https://patch.msgid.link/20250322-tn9510-v3a-v7-6-672a9a3d8628@gmx.net
Signed-off-by: Jakub Kicinski

net: tn40xx: create swnode for mdio and aqr105 phy and add to mdiobus

2025-03-25T20:53:21+00:00

In case of an AQR105-based device, create a software node for the mdio
function, with a child node for the Aquantia AQR105 PHY, providing a
firmware-name (and a bit more, which may be used for future checks) to
allow the PHY to load a MAC specific firmware from the file system.

The name of the PHY software node follows the naming convention suggested
in the patch for the mdiobus_scan function (in the same patch series).

Signed-off-by: Hans-Frieder Vogt 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20250322-tn9510-v3a-v7-5-672a9a3d8628@gmx.net
Signed-off-by: Jakub Kicinski

netdev_features: convert NETIF_F_LLTX to dev->lltx

2024-09-03T09:36:43+00:00

NETIF_F_LLTX can't be changed via Ethtool and is not a feature,
rather an attribute, very similar to IFF_NO_QUEUE (and hot).
Free one netdev_features_t bit and make it a "hot" private flag.

Signed-off-by: Alexander Lobakin 
Signed-off-by: Paolo Abeni

net: tn40xx: add per queue netdev-genl stats support

2024-07-09T11:26:57+00:00

Add support for the netdev-genl per queue stats API.

./tools/net/ynl/cli.py --spec Documentation/netlink/specs/netdev.yaml \
--dump qstats-get --json '{"scope":"queue"}'
[{'ifindex': 4,
  'queue-id': 0,
  'queue-type': 'rx',
  'rx-alloc-fail': 0,
  'rx-bytes': 266613,
  'rx-packets': 3325},
 {'ifindex': 4,
  'queue-id': 0,
  'queue-type': 'tx',
  'tx-bytes': 142823367,
  'tx-packets': 2387}]

Signed-off-by: FUJITA Tomonori 
Reviewed-by: Jakub Kicinski 
Link: https://patch.msgid.link/20240706064324.137574-1-fujita.tomonori@gmail.com
Signed-off-by: Paolo Abeni

net: tn40xx: add initial ethtool_ops support

2024-07-01T10:00:39+00:00

Call phylink_ethtool_ksettings_get() for get_link_ksettings method and
ethtool_op_get_link() for get_link method.

Signed-off-by: FUJITA Tomonori 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: tn40xx: add phylink support

2024-06-26T01:44:19+00:00

This patch adds supports for multiple PHY hardware with phylink. The
adapters with TN40xx chips use multiple PHY hardware; AMCC QT2025, TI
TLK10232, Aqrate AQR105, and Marvell 88X3120, 88X3310, and MV88E2010.

For now, the PCI ID table of this driver enables adapters using only
QT2025 PHY. I've tested this driver and the QT2025 PHY driver (SFP+
10G SR) with Edimax EN-9320 10G adapter.

Signed-off-by: FUJITA Tomonori 
Reviewed-by: Hans-Frieder Vogt 
Reviewed-by: Russell King (Oracle) 
Link: https://patch.msgid.link/20240623235507.108147-8-fujita.tomonori@gmail.com
Signed-off-by: Jakub Kicinski

net: tn40xx: add mdio bus support

2024-06-26T01:44:19+00:00

This patch adds supports for mdio bus. A later path adds PHYLIB
support on the top of this.

Signed-off-by: FUJITA Tomonori 
Link: https://patch.msgid.link/20240623235507.108147-7-fujita.tomonori@gmail.com
Signed-off-by: Jakub Kicinski

net: tn40xx: add basic Rx handling

2024-06-26T01:44:19+00:00

This patch adds basic Rx handling. The Rx logic uses three major data
structures; two ring buffers with NIC and one database. One ring
buffer is used to send information to NIC about memory to be stored
packets to be received. The other is used to get information from NIC
about received packets. The database is used to keep the information
about DMA mapping. After a packet arrived, the db is used to pass the
packet to the network stack.

Signed-off-by: FUJITA Tomonori 
Reviewed-by: Hans-Frieder Vogt 
Link: https://patch.msgid.link/20240623235507.108147-6-fujita.tomonori@gmail.com
Signed-off-by: Jakub Kicinski