linux-toradex.git/drivers/net/ixgbe/ixgbe_dcb.c, branch v3.0.5 Linux kernel for Apalis and Colibri modules Fix common misspellings 2011-03-31T14:26:23+00:00 Lucas De Marchi lucas.demarchi@profusion.mobi 2011-03-31T01:57:33+00:00 25985edcedea6396277003854657b5f3cb31a628 Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi> 
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
ixgbe: DCB, set minimum bandwidth per traffic class 2011-03-12T12:14:48+00:00 John Fastabend john.r.fastabend@intel.com 2011-03-09T04:46:16+00:00 1390a59452a0895d3fea5b5504fa75ba36c13a74 DCB provides a guaranteed bandwidth in the case with 0% bandwidth then no bandwidth is guaranteed. However the traffic class should still be able to transmit traffic. For this to work the traffic class must be given the minimum credits required to send a frame. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> 
DCB provides a guaranteed bandwidth in the case with 0%
bandwidth then no bandwidth is guaranteed. However the
traffic class should still be able to transmit traffic.
For this to work the traffic class must be given the
minimum credits required to send a frame.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
ixgbe: IEEE 802.1Qaz, implement priority assignment table 2011-03-12T12:12:54+00:00 John Fastabend john.r.fastabend@intel.com 2011-02-23T05:58:19+00:00 17049d30c2dec6f26d6165cc135578f9e41d53d3 This patch adds support to use the priority assignment table in the ieee_ets structure to map priorities to traffic classes. Previously ixgbe only supported a 1:1 mapping. Now we can enable and disable hardware DCB support when multiple traffic classes are actually being used. This allows the default case all priorities mapped to traffic class 0 to work in normal hardware mode and utilize the full packet buffer. This patch does not address putting the hardware in 4TC mode so packet buffer space may be underutilized in this case. A follow up patch can address this optimization. But at least we have the hooks to do this now. Also CEE will behave as it always has and map priorities 1:1 with traffic classes. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> 
This patch adds support to use the priority assignment
table in the ieee_ets structure to map priorities to
traffic classes. Previously ixgbe only supported a
1:1 mapping. Now we can enable and disable hardware
DCB support when multiple traffic classes are actually
being used. This allows the default case all priorities
mapped to traffic class 0 to work in normal hardware
mode and utilize the full packet buffer.

This patch does not address putting the hardware in
4TC mode so packet buffer space may be underutilized
in this case. A follow up patch can address this
optimization. But at least we have the hooks to do
this now.

Also CEE will behave as it always has and map priorities
1:1 with traffic classes.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
ixgbe: DCB, missed translation from 8021Qaz TSA to CEE link strict 2011-03-12T12:12:35+00:00 John Fastabend john.r.fastabend@intel.com 2011-02-23T05:58:14+00:00 3b97fd695453ced96f22bdf1a84453f6744d25cc The patch below allowed IEEE 802.1Qaz and CEE DCB hardware configurations to use common hardware set routines, commit 88eb696cc6a7af8f9272266965b1a4dd7d6a931b Author: John Fastabend <john.r.fastabend@intel.com> Date: Thu Feb 10 03:02:11 2011 -0800 ixgbe: DCB, abstract out dcb_config from DCB hardware configuration However the case when CEE link strict and group strict are set was missed and are currently being mapped incorrectly in some configurations. This patch resolves this. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> 
The patch below  allowed IEEE 802.1Qaz and CEE DCB hardware
configurations to use common hardware set routines,

commit 88eb696cc6a7af8f9272266965b1a4dd7d6a931b
Author: John Fastabend <john.r.fastabend@intel.com>
Date:   Thu Feb 10 03:02:11 2011 -0800

    ixgbe: DCB, abstract out dcb_config from DCB hardware configuration

However the case when CEE link strict and group strict
are set was missed and are currently being mapped
incorrectly in some configurations.

This patch resolves this.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
ixgbe: cleanup copyright string for 2011 2011-03-03T12:43:24+00:00 Don Skidmore donald.c.skidmore@intel.com 2011-02-23T09:58:39+00:00 a52055e055f5b551c0814c4381e43b204f9db777 Updating the copyrights for 2011 as well as make the ixgbe_copyright string a constant. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> 
Updating the copyrights for 2011 as well as make the ixgbe_copyright string
a constant.

Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
ixgbe: DCB, implement 802.1Qaz routines 2011-02-11T16:47:15+00:00 John Fastabend john.r.fastabend@intel.com 2011-02-10T14:40:01+00:00 d033d526a465c4bb8a499a0b5df65b3e7cf4da6f Implements 802.1Qaz support for ixgbe driver. Additionally, this adds IEEE_8021QAZ_TSA_{} defines to dcbnl.h this is to avoid having to use cryptic numeric codes for the TSA type. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> 
Implements 802.1Qaz support for ixgbe driver. Additionally,
this adds IEEE_8021QAZ_TSA_{} defines to dcbnl.h this is to
avoid having to use cryptic numeric codes for the TSA type.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
ixgbe: DCB, abstract out dcb_config from DCB hardware configuration 2011-02-11T16:44:04+00:00 John Fastabend john.r.fastabend@intel.com 2011-01-05T04:47:43+00:00 55320cb58baebd1795ec92f4550a1e8b38bf9ddf Currently the routines that configure the HW for DCB require a ixgbe_dcb_config structure. This structure was designed to support the CEE standard and does not match the IEEE standard well. This patch changes the HW routines in ixgbe_dcb_8259x.{ch} to use raw pfc and bandwidth values. This requires some parsing of the DCB configuration but makes the HW routines independent of the data structure that contains the DCB configuration. The primary advantage to doing this is we can do HW setup directly from the 802.1Qaz ops without having to arbitrarily encapsulate this data into the CEE structure. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> 
Currently the routines that configure the HW for DCB require a
ixgbe_dcb_config structure. This structure was designed to support
the CEE standard and does not match the IEEE standard well.

This patch changes the HW routines in ixgbe_dcb_8259x.{ch} to use
raw pfc and bandwidth values. This requires some parsing of the DCB
configuration but makes the HW routines independent of the data
structure that contains the DCB configuration.

The primary advantage to doing this is we can do HW setup directly
from the 802.1Qaz ops without having to arbitrarily encapsulate this
data into the CEE structure.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
ixgbe: add support for x540 MAC 2010-11-17T03:27:17+00:00 Don Skidmore donald.c.skidmore@intel.com 2010-11-17T03:27:17+00:00 b93a22260f6f4bcf6c92c54de8530a97d3e921f0 This patch adds support for the x540 MAC which is the next MAC in the 82598/82599 line. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> 
This patch adds support for the x540 MAC which is the next MAC in the
82598/82599 line.

Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
ixgbe: DCB: credit max only needs to be gt TSO size for 82598 2010-11-17T03:26:45+00:00 John Fastabend john.r.fastabend@intel.com 2010-11-17T03:26:45+00:00 80ab193dce048e7b7afa43c99e69f508167e29ab The maximum credits per traffic class only needs to be greater then the TSO size for 82598 devices. The 82599 devices do not have this requirement so only do this test for 82598 devices. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> 
The maximum credits per traffic class only needs to be greater
then the TSO size for 82598 devices. The 82599 devices do not
have this requirement so only do this test for 82598 devices.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
ixgbe: DCB, fix TX hang occurring in stress condition with PFC 2010-10-28T17:19:00+00:00 John Fastabend john.r.fastabend@intel.com 2010-10-28T00:59:57+00:00 9806307a1c5a2a79e268ae4e78b437d38c8adf7f The DCB credits refill quantum _must_ be greater than half the max packet size. This is needed to guarantee that TX DMA operations are not attempted during a pause state. Additionally, the min IFG must be set correctly for DCB mode. If a DMA operation is requested unexpectedly during the pause state the HW data store may be corrupted leading to a DMA hang. The DMA hang requires a reset to correct. This fixes the HW configuration to avoid this condition. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
The DCB credits refill quantum _must_ be greater than half the max
packet size. This is needed to guarantee that TX DMA operations
are not attempted during a pause state. Additionally, the min IFG
must be set correctly for DCB mode. If a DMA operation is
requested unexpectedly during the pause state the HW data
store may be corrupted leading to a DMA hang.  The DMA hang
requires a reset to correct. This fixes the HW configuration
to avoid this condition.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>