linux-toradex.git/drivers/net/jme.h, branch tegra-9.12.13 Linux kernel for Apalis and Colibri modules Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6 2008-12-24T01:56:23+00:00 David S. Miller davem@davemloft.net 2008-12-24T01:56:23+00:00 6332178d91ca1a9dbd99bd97cabbcf965d178e9f Conflicts: drivers/net/ppp_generic.c 
Conflicts:

	drivers/net/ppp_generic.c
net: Remove unused netdev arg from some NAPI interfaces. 2008-12-23T04:43:12+00:00 Neil Horman nhorman@tuxdriver.com 2008-12-23T04:43:12+00:00 908a7a16b852ffd618a9127be8d62432182d81b4 When the napi api was changed to separate its 1:1 binding to the net_device struct, the netif_rx_[prep|schedule|complete] api failed to remove the now vestigual net_device structure parameter. This patch cleans up that api by properly removing it.. Signed-off-by: Neil Horman <nhorman@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
When the napi api was changed to separate its 1:1 binding to the net_device
struct, the netif_rx_[prep|schedule|complete] api failed to remove the now
vestigual net_device structure parameter.  This patch cleans up that api by
properly removing it..

Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
jme: Fixed a typo 2008-12-17T08:26:37+00:00 cwm97m cwm97m@cse.nsysu.edu.tw 2008-12-16T20:28:44+00:00 2fccd2814f8ebc8f1bd325dc46e11c333fc76ab3 Found a typo. Signed-off-by: Wei-Min Chen <cwm97m@cse.nsysu.edu.tw> Signed-off-by: David S. Miller <davem@davemloft.net> 
Found a typo.

Signed-off-by: Wei-Min Chen <cwm97m@cse.nsysu.edu.tw>
Signed-off-by: David S. Miller <davem@davemloft.net>
jme: GHC register control fix for new hardware 2008-12-04T05:19:16+00:00 akeemting akeem@jmicron.com 2008-12-04T05:19:16+00:00 4f40bf46897ddb57f149c0758f0cef0cc7782f7f Due to the hardware design, except the first chip on the market, other chips needs to setup the clock source for MAC processor implicitly through Global Host Control Register(GHC). (Strange design huh?) 10/100M uses the PCI-E as clock source, and 1G uses GPHY. And I reordered the code a little, to make it easier to read. Found-by: "Ethan" <ethanhsiao@jmicron.com> Fixed-by: "akeemting" <akeem@jmicron.com> Signed-off-by: "Guo-Fu Tseng" <cooldavid@cooldavid.org> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
Due to the hardware design, except the first chip on the market,
other chips needs to setup the clock source for MAC processor
implicitly through Global Host Control Register(GHC).
(Strange design huh?)

10/100M uses the PCI-E as clock source, and 1G uses GPHY.

And I reordered the code a little, to make it easier to read.

Found-by: "Ethan" <ethanhsiao@jmicron.com>
Fixed-by: "akeemting" <akeem@jmicron.com>
Signed-off-by: "Guo-Fu Tseng" <cooldavid@cooldavid.org>
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
jme: Advances version number 2008-10-09T02:51:33+00:00 Guo-Fu Tseng cooldavid@cooldavid.org 2008-10-09T02:50:44+00:00 6dc0c97fdcf63cf65a5857ad739a41f9eac9f2fc Advances the driver version after modification. Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org> Signed-off-by: David S. Miller <davem@davemloft.net> 
Advances the driver version after modification.

Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
jme: Added half-duplex mode and IPv6 RSS fix 2008-10-09T02:51:31+00:00 Guo-Fu Tseng cooldavid@cooldavid.org 2008-10-09T02:48:58+00:00 a821ebe580c535e3e8e354c6ab10516a0e95e202 1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex mode. Which the MAC processor generates CRS/COL by itself instead of receive it from PHY processor. 2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the MAC processor working right while calculating IPv6 RSS in 10/100 mode. 3. Group the workaround codes all together. Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org> Signed-off-by: David S. Miller <davem@davemloft.net> 
1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex
   mode. Which the MAC processor generates CRS/COL by itself instead of
   receive it from PHY processor.

2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the
   MAC processor working right while calculating IPv6 RSS in 10/100
   mode.

3. Group the workaround codes all together.

Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
jme: JMicron Gigabit Ethernet Driver 2008-09-18T15:34:54+00:00 Guo-Fu Tseng cooldavid@cooldavid.org 2008-09-15T17:00:11+00:00 95252236e73e789dd186ce796a2abc60b3a61ebe Supporting JMC250, and JMC260. Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org> Acked-and-tested-by: Ethan Hsiao <ethanhsiao@jmicron.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> 
Supporting JMC250, and JMC260.

Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Acked-and-tested-by: Ethan Hsiao <ethanhsiao@jmicron.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>