linux-toradex.git/drivers/net/phy/dp83867.c, branch v4.16-rc4

net: phy: remove generic settings for callbacks config_aneg and read_status from drivers

2017-12-01T20:42:21+00:00

Remove generic settings for callbacks config_aneg and read_status
from drivers.

Signed-off-by: Heiner Kallweit 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap

2017-07-05T08:23:53+00:00

The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
supported (see note below Table 5 (4-Level Strap Pins)).

There are some boards which have the pin strapped this way and need
software workaround suggested by the data manual. Bit[7] of
Configuration Register 4 (address 0x0031) must be cleared to 0. This
ensures proper operation of the PHY.

Implement driver support for device-tree property meant to advertise
the wrong strapping.

[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf

Signed-off-by: Murali Karicheri 
[nsekhar@ti.com: rebase to mainline, code simplification]
Signed-off-by: Sekhar Nori 
Signed-off-by: David S. Miller

net: phy: switch remaining users to phy_(read|write)_mmd()

2017-03-22T19:43:00+00:00

Switch everyone over to using phy_read_mmd() and phy_write_mmd() now
that they are able to handle both Clause 22 indirect addressing and
Clause 45 direct addressing methods to the MMD registers.

Reviewed-by: Andrew Lunn 
Reviewed-by: Florian Fainelli 
Signed-off-by: Russell King 
Signed-off-by: David S. Miller

net: phy: dp83867: Recover from "port mirroring" N/A MODE4

2017-02-07T18:59:27+00:00

The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.

To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).

To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.

Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"

https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954

Signed-off-by: Lukasz Majewski 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver

2017-02-07T18:59:27+00:00

This patch adds support for enabling or disabling the lane swapping (called
"port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY
device.

One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).

Signed-off-by: Lukasz Majewski 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: dp83867: allow RGMII_TXID/RGMII_RXID interface types

2017-01-16T18:29:51+00:00

Currently dp83867 driver returns error if phy interface type
PHY_INTERFACE_MODE_RGMII_RXID is used to set the rx only internal
delay. Similarly issue happens for PHY_INTERFACE_MODE_RGMII_TXID.
Fix this by checking also the interface type if a particular delay
value is missing in the phy dt bindings. Also update the DT document
accordingly.

Signed-off-by: Murali Karicheri 
Signed-off-by: Sekhar Nori 
Signed-off-by: David S. Miller

net: phy: dp83867: fix irq generation

2017-01-06T20:52:43+00:00

For proper IRQ generation by DP83867 phy the INT/PWDN pin has to be
programmed as an interrupt output instead of a Powerdown input in
Configuration Register 3 (CFG3), Address 0x001E, bit 7 INT_OE = 1. The
current driver doesn't do this and as result IRQs will not be generated by
DP83867 phy even if they are properly configured in DT.

Hence, fix IRQ generation by properly configuring CFG3.INT_OE bit and
ensure that Link Status Change (LINK_STATUS_CHNG_INT) and Auto-Negotiation
Complete (AUTONEG_COMP_INT) interrupt are enabled. After this the DP83867
driver will work properly in interrupt enabled mode.

Signed-off-by: Grygorii Strashko 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: dp83867: add support for MAC impedance configuration

2016-10-18T14:42:16+00:00

Add support for programmable MAC impedance configuration

Signed-off-by: Mugunthan V N 
Signed-off-by: David S. Miller

net: phy: dp83867: Fix initialization of PHYCR register

2016-07-02T18:48:58+00:00

When initializing the PHY control register, the FIFO depth bits are
written without reading the previous register value, i.e. all other
bits are overwritten with zero. This disables automatic MDI-X
configuration, which is enabled by default. Fix initialization by doing
a read/modify/write operation.

Signed-off-by: Stefan Hauser 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

phy: Centralize setting driver module owner

2016-01-07T19:31:27+00:00

Rather than have each driver set the driver owner field, do it once in
the core code. This will also help with later changes, when the device
structure will move.

Signed-off-by: Andrew Lunn 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller