linux-toradex.git/drivers/net/phy, branch v5.10-rc3

sfp: Fix error handing in sfp_probe()

2020-11-03T01:19:59+00:00

gpiod_to_irq() never return 0, but returns negative in
case of error, check it and set gpio_irq to 0.

Fixes: 73970055450e ("sfp: add SFP module support")
Signed-off-by: YueHaibing 
Reviewed-by: Andrew Lunn 
Link: https://lore.kernel.org/r/20201031031053.25264-1-yuehaibing@huawei.com
Signed-off-by: Jakub Kicinski

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

2020-10-06T01:40:01+00:00

Rejecting non-native endian BTF overlapped with the addition
of support for it.

The rest were more simple overlapping changes, except the
renesas ravb binding update, which had to follow a file
move as well as a YAML conversion.

Signed-off-by: David S. Miller

net: phy: marvell: Use phy_read_paged() instead of open coding it

2020-10-05T13:12:10+00:00

Convert m88e1318_get_wol() to use the well implemented phy_read_paged()
instead of open coding it.

Signed-off-by: Jisheng Zhang 
Reviewed-by: Marek Behún 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: dp83869: fix unsigned comparisons against less than zero values

2020-10-04T00:08:32+00:00

Currently the comparisons of u16 integers value and sopass_val with
less than zero for error checking is always false because the values
are unsigned. Fix this by making these variables int.  This does not
affect the shift and mask operations performed on these variables

Addresses-Coverity: ("Unsigned compared against zero")
Fixes: 49fc23018ec6 ("net: phy: dp83869: support Wake on LAN")
Signed-off-by: Colin Ian King 
Acked-by: Dan Murphy 
Signed-off-by: David S. Miller

net: phy: realtek: Modify 2.5G PHY name to RTL8226

2020-10-02T01:49:47+00:00

Realtek single-chip Ethernet PHY solutions can be separated as below:
10M/100Mbps: RTL8201X
1Gbps: RTL8211X
2.5Gbps: RTL8226/RTL8221X
RTL8226 is the first version for realtek that compatible 2.5Gbps single PHY.
Since RTL8226 is single port only, realtek changes its name to RTL8221B from
the second version.
PHY ID for RTL8226 is 0x001cc800 and RTL8226B/RTL8221B is 0x001cc840.

RTL8125 is not a single PHY solution, it integrates PHY/MAC/PCIE bus
controller and embedded memory.

Signed-off-by: Willy Liu 
Signed-off-by: David S. Miller

net: mdiobus: Remove WARN_ON_ONCE(in_interrupt())

2020-09-29T21:02:54+00:00

in_interrupt() is ill defined and does not provide what the name
suggests. The usage especially in driver code is deprecated and a tree wide
effort to clean up and consolidate the (ab)usage of in_interrupt() and
related checks is happening.

In this case the check covers only parts of the contexts in which these
functions cannot be called. It fails to detect preemption or interrupt
disabled invocations.

As the functions which contain these warnings invoke mutex_lock() which
contains a broad variety of checks (always enabled or debug option
dependent) and therefore covers all invalid conditions already, there is no
point in having inconsistent warnings in those drivers. The conditional
return is not really valuable in practice either.

Just remove them.

Signed-off-by: Sebastian Andrzej Siewior 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: realtek: fix rtl8211e rx/tx delay config

2020-09-29T19:55:33+00:00

There are two chip pins named TXDLY and RXDLY which actually adds the 2ns
delays to TXC and RXC for TXD/RXD latching. These two pins can config via
4.7k-ohm resistor to 3.3V hw setting, but also config via software setting
(extension page 0xa4 register 0x1c bit13 12 and 11).

The configuration register definitions from table 13 official PHY datasheet:
PHYAD[2:0] = PHY Address
AN[1:0] = Auto-Negotiation
Mode = Interface Mode Select
RX Delay = RX Delay
TX Delay = TX Delay
SELRGV = RGMII/GMII Selection

This table describes how to config these hw pins via external pull-high or pull-
low resistor.

It is a misunderstanding that mapping it as register bits below:
8:6 = PHY Address
5:4 = Auto-Negotiation
3 = Interface Mode Select
2 = RX Delay
1 = TX Delay
0 = SELRGV
So I removed these descriptions above and add related settings as below:
14 = reserved
13 = force Tx RX Delay controlled by bit12 bit11
12 = Tx Delay
11 = Rx Delay
10:0 = Test && debug settings reserved by realtek

Test && debug settings are not recommend to modify by default.

Fixes: f81dadbcf7fd ("net: phy: realtek: Add rtl8211e rx/tx delays config")
Signed-off-by: Willy Liu 
Signed-off-by: David S. Miller

net: Use kobj_to_dev() API

2020-09-28T22:14:42+00:00

Use kobj_to_dev() instead of container_of().

Signed-off-by: Wang Qing 
Signed-off-by: David S. Miller

net: phy: dp83869: Add speed optimization feature

2020-09-28T19:44:12+00:00

Set the speed optimization bit on the DP83869 PHY.

Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).

The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.

Signed-off-by: Dan Murphy 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: dp83869: support Wake on LAN

2020-09-28T19:44:12+00:00

This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.

Signed-off-by: Dan Murphy 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller