linux-toradex.git/drivers/ntb, branch v5.1-rc1

Merge tag 'ntb-5.1' of git://github.com/jonmason/ntb

2019-03-15T21:32:59+00:00

Pull NTB updates from Jon Mason:

 - fixes for switchtec debugability and mapping table entries

 - NTB transport improvements

 - a reworking of the peer_db_addr for better abstraction

* tag 'ntb-5.1' of git://github.com/jonmason/ntb:
  NTB: add new parameter to peer_db_addr() db_bit and db_data
  NTB: ntb_transport: Ensure the destination buffer is mapped for TX DMA
  NTB: ntb_transport: Free MWs in ntb_transport_link_cleanup()
  ntb_hw_switchtec: Added support of >=4G memory windows
  ntb_hw_switchtec: NT req id mapping table register entry number should be 512
  ntb_hw_switchtec: debug print 64bit aligned crosslink BAR Numbers

NTB: add new parameter to peer_db_addr() db_bit and db_data

2019-02-13T16:03:18+00:00

NTB door bell usage depends on NTB hardware.

ex: intel NTB gen1 has one peer door bell register which can be controlled
by the bitmap writen to it, while Intel NTB gen3 has a registers
per door bell and the data trigering the each door bell is always 1.

therefore exposing only peer door bell address forcing the user
to be aware of such low level details

Signed-off-by: Leonid Ravich 
Acked-by: Logan Gunthorpe 
Acked-by: Dave Jiang 
Acked-by: Allen Hubbe 
Signed-off-by: Jon Mason

NTB: ntb_transport: Ensure the destination buffer is mapped for TX DMA

2019-02-11T14:26:30+00:00

Presently, when ntb_transport is used with DMA and the IOMMU turned on,
it fails with errors from the IOMMU such as:

  DMAR: DRHD: handling fault status reg 202
  DMAR: [DMA Write] Request device [00:04.0] fault addr
	381fc0340000 [fault reason 05] PTE Write access is not set

This is because ntb_transport does not map the BAR space with the IOMMU.

To fix this, we map the entire MW region for each QP after we assign
the DMA channel. This prevents needing an extra DMA map in the fast
path.

Link: https://lore.kernel.org/linux-pci/499934e7-3734-1aee-37dd-b42a5d2a2608@intel.com/
Signed-off-by: Logan Gunthorpe 
Reviewed-by: Dave Jiang 
Signed-off-by: Jon Mason

NTB: ntb_transport: Free MWs in ntb_transport_link_cleanup()

2019-02-11T14:26:05+00:00

If NTB peer host crashes or reboots, the NTB transport link will be
down and the MWs of NTB transport will be invalid. But the
ntb_transport_link_cleanup() does not free these invalid MWs. When
the NTB peer host is recovered later, NTB transport link will be
up and the ntb_set_mw() will not reset up MWs. Because the MWs of
NTB transport are invalid, the NTB transport will not work.

We can fix it by freeing MWs when NTB transport link is down, then
the ntb_set_mw() will reset up MWs when NTB transport link is up.

Signed-off-by: Joey Zhang 
Reviewed-by: Logan Gunthorpe 
Signed-off-by: Jon Mason

ntb_hw_switchtec: Added support of >=4G memory windows

2019-02-11T12:36:13+00:00

Current Switchtec's BAR setup registers are limited to 32bits,
corresponding to the maximum MW (memory window) size is <4G.

Increase the MW sizes with the addition of the BAR Setup Extension
Register for the upper 32bits of a 64bits MW size. This increases the MW
range to between 4K and 2^63.

Reported-by: Boris Glimcher 
Signed-off-by: Paul Selles 
Signed-off-by: Wesley Sheng 
Reviewed-by: Logan Gunthorpe 
Signed-off-by: Jon Mason

ntb_hw_switchtec: debug print 64bit aligned crosslink BAR Numbers

2019-02-11T12:36:13+00:00

Switchtec NTB crosslink BARs are 64bit addressed but they are printed as
32bit addressed BARs. Fix debug log to increment the BAR numbers by 2 to
reflect the 64bit address alignment.

Fixes: 017525018202 ("ntb_hw_switchtec: Add initialization code for crosslink")
Signed-off-by: Paul Selles 
Signed-off-by: Wesley Sheng 
Reviewed-by: Logan Gunthorpe 
Signed-off-by: Jon Mason

Merge 5.0-rc4 into char-misc-next

2019-01-28T07:13:52+00:00

We need the char-misc fixes in here as well.

Signed-off-by: Greg Kroah-Hartman

ntb: ntb_hw_switchtec: Cleanup 64bit IO defines to use the common header

2019-01-22T12:40:00+00:00

Clean up the ifdefs which conditionally defined the io{read|write}64
functions in favour of the new common io-64-nonatomic-lo-hi header.

Per a nit from Andy Shevchenko, the include list is also made
alphabetical.

Signed-off-by: Logan Gunthorpe 
Reviewed-by: Andy Shevchenko 
Cc: Jon Mason 
Signed-off-by: Greg Kroah-Hartman

ntb: ntb_hw_intel: use io-64-nonatomic instead of in-driver hacks

2019-01-22T12:39:59+00:00

Now that ioread64 and iowrite64 are available in io-64-nonatomic,
we can remove the hack at the top of ntb_hw_intel.c and replace it
with an include.

Signed-off-by: Logan Gunthorpe 
Reviewed-by: Andy Shevchenko 
Acked-by: Dave Jiang 
Acked-by: Allen Hubbe 
Acked-by: Jon Mason 
Signed-off-by: Greg Kroah-Hartman

cross-tree: phase out dma_zalloc_coherent()

2019-01-08T12:58:37+00:00

We already need to zero out memory for dma_alloc_coherent(), as such
using dma_zalloc_coherent() is superflous. Phase it out.

This change was generated with the following Coccinelle SmPL patch:

@ replace_dma_zalloc_coherent @
expression dev, size, data, handle, flags;
@@

-dma_zalloc_coherent(dev, size, handle, flags)
+dma_alloc_coherent(dev, size, handle, flags)

Suggested-by: Christoph Hellwig 
Signed-off-by: Luis Chamberlain 
[hch: re-ran the script on the latest tree]
Signed-off-by: Christoph Hellwig