linux-toradex.git/drivers/nvmem/Kconfig, branch v5.0

nvmem: Add Spreadtrum SC27XX efuse support

2018-07-15T12:03:05+00:00

This patch add the efuse driver which is embeded in Spreadtrum SC27XX
series PMICs. The sc27xx efuse contains 32 blocks and each block's
data width is 16 bits.

Signed-off-by: Freeman Liu 
Signed-off-by: Baolin Wang 
Signed-off-by: Srinivas Kandagatla 
Signed-off-by: Greg Kroah-Hartman

nvmem: Add RAVE SP EEPROM driver

2018-05-14T14:20:48+00:00

Add driver providing access to EEPROMs connected to RAVE SP devices

Cc: Srinivas Kandagatla 
Cc: linux-kernel@vger.kernel.org
Cc: Chris Healy 
Cc: Lucas Stach 
Cc: Aleksander Morgado 
Signed-off-by: Andrey Smirnov 
Signed-off-by: Srinivas Kandagatla 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'char-misc-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

2018-04-05T03:07:20+00:00

Pull char/misc updates from Greg KH:
 "Here is the big set of char/misc driver patches for 4.17-rc1.

  There are a lot of little things in here, nothing huge, but all
  important to the different hardware types involved:

   -  thunderbolt driver updates

   -  parport updates (people still care...)

   -  nvmem driver updates

   -  mei updates (as always)

   -  hwtracing driver updates

   -  hyperv driver updates

   -  extcon driver updates

   -  ... and a handful of even smaller driver subsystem and individual
      driver updates

  All of these have been in linux-next with no reported issues"

* tag 'char-misc-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (149 commits)
  hwtracing: Add HW tracing support menu
  intel_th: Add ACPI glue layer
  intel_th: Allow forcing host mode through drvdata
  intel_th: Pick up irq number from resources
  intel_th: Don't touch switch routing in host mode
  intel_th: Use correct method of finding hub
  intel_th: Add SPDX GPL-2.0 header to replace GPLv2 boilerplate
  stm class: Make dummy's master/channel ranges configurable
  stm class: Add SPDX GPL-2.0 header to replace GPLv2 boilerplate
  MAINTAINERS: Bestow upon myself the care for drivers/hwtracing
  hv: add SPDX license id to Kconfig
  hv: add SPDX license to trace
  Drivers: hv: vmbus: do not mark HV_PCIE as perf_device
  Drivers: hv: vmbus: respect what we get from hv_get_synint_state()
  /dev/mem: Avoid overwriting "err" in read_mem()
  eeprom: at24: use SPDX identifier instead of GPL boiler-plate
  eeprom: at24: simplify the i2c functionality checking
  eeprom: at24: fix a line break
  eeprom: at24: tweak newlines
  eeprom: at24: refactor at24_probe()
  ...

nvmem: disallow modular CONFIG_NVMEM

2018-04-04T15:47:50+00:00

The new of_get_nvmem_mac_address() helper function causes a link error
with CONFIG_NVMEM=m:

drivers/of/of_net.o: In function `of_get_nvmem_mac_address':
of_net.c:(.text+0x168): undefined reference to `of_nvmem_cell_get'
of_net.c:(.text+0x19c): undefined reference to `nvmem_cell_read'
of_net.c:(.text+0x1a8): undefined reference to `nvmem_cell_put'

I could not come up with a good solution for this, as the code is always
built-in. Using an #if IS_REACHABLE() check around it would solve the
link time issue but then stop it from working in that configuration.
Making of_nvmem_cell_get() an inline function could also solve that, but
seems a bit ugly since it's somewhat larger than most inline functions,
and it would just bring that problem into the callers.  Splitting the
function into a separate file might be an alternative.

This uses the big hammer by making CONFIG_NVMEM itself a 'bool' symbol,
which avoids the problem entirely but makes the vmlinux larger for anyone
that might use NVMEM support but doesn't need it built-in otherwise.

Fixes: 9217e566bdee ("of_net: Implement of_get_nvmem_mac_address helper")
Cc: Mike Looijmans 
Cc: Florian Fainelli 
Cc: Andrew Lunn 
Cc: David S. Miller 
Cc: netdev@vger.kernel.org
Signed-off-by: Arnd Bergmann 
Acked-by: Mike Looijmans
Signed-off-by: David S. Miller

nvmem: add i.MX7 support to snvs-lpgpr

2018-03-14T18:28:14+00:00

The i.MX7 family has similar SNVS hardware so make the snvs-lpgpr
support it along with the i.MX6 family. The register interface is the
same except for the number and offset of the general purpose registers.

Signed-off-by: Andrey Yurovsky 
Reviewed-by: Oleksij Rempel 
Signed-off-by: Srinivas Kandagatla 
Signed-off-by: Greg Kroah-Hartman

nvmem: uniphier: add UniPhier eFuse driver

2017-11-08T13:19:05+00:00

Add eFuse driver for Socionext UniPhier series SoC.
Note that eFuse device is under soc-glue and this register
implements as read only.

Signed-off-by: Keiji Hayashibara 
Signed-off-by: Srinivas Kandagatla 
Signed-off-by: Greg Kroah-Hartman

nvmem: add a driver for the Amlogic Meson6/Meson8/Meson8b SoCs

2017-10-20T13:38:02+00:00

This adds a driver to access the efuse on Amlogic Meson6, Meson8 and
Meson8b SoCs.
These SoCs are accessing the efuse IP block directly through the
registers in the "secbus" region. This makes it different from the Meson
GX efuse driver which uses the "secure monitor" firmware to access the
efuse.

The efuse on Meson6 can only read one byte at a time, while the efuse on
Meson8 and Meson8b always reads 4 bytes at a time. The new driver
supports both, but due to lack of hardware Meson6 support was not tested.

The hardware also supports writing. However, this is currently not
supported by the driver.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Srinivas Kandagatla 
Signed-off-by: Greg Kroah-Hartman

nvmem: meson-efuse: indicate that this driver is only for Meson GX SoCs

2017-10-20T13:38:02+00:00

The current Amlogic Meson eFuse driver only supports the 64-bit SoCs
(GXBB and newer). Older SoCs cannot be supported by the same driver
because they do not use the meson secure monitor firmware to access the
hardware.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Srinivas Kandagatla 
Acked-by: Rob Herring 
Signed-off-by: Greg Kroah-Hartman

nvmem: add snvs_lpgpr driver

2017-10-04T08:30:53+00:00

This is a driver for Low Power General Purpose Register (LPGPR)
available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS)
of this chip.

It is a 32-bit read/write register located in the low power domain.
Since LPGPR is located in the battery-backed power domain, LPGPR can
be used by any application for retaining data during an SoC power-down
mode.

Signed-off-by: Oleksij Rempel 
Signed-off-by: Srinivas Kandagatla 
Signed-off-by: Greg Kroah-Hartman

nvmem: Add driver for the i.MX IIM

2017-04-08T15:51:48+00:00

This adds a readonly nvmem driver for the i.MX IC Identification Module
(IIM). The IIM is found on the older i.MX SoCs like the i.MX25, i.MX27,
i.MX31, i.MX35, i.MX51 and the i.MX53.

The IIM can control up to 8 fuse banks with 256 bit each. Not all of the
banks are equipped on the different SoCs. The actual number of fuses
differ from 512 on the i.MX27 and 1152 on the i.MX53.

The fuses are one time writable, but writing is currently not supported
in the driver.

Signed-off-by: Michael Grzeschik 
Signed-off-by: Sascha Hauer 
Signed-off-by: Srinivas Kandagatla 
Signed-off-by: Greg Kroah-Hartman