linux-toradex.git/drivers/pci/controller/cadence/Kconfig, branch master Linux kernel for Apalis and Colibri modules PCI: sky1: Add PCIe host support for CIX Sky1 2025-12-02T20:17:55+00:00 Hans Zhang hans.zhang@cixtech.com 2025-11-08T14:03:02+00:00 a0d9f2c08f45ff3dfdb9eb0a843a486ad4875dbe Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based on the Cadence High Performance Architecture (HPA) PCIe core. The controller supports MSI/MSI-X via GICv3, Single Virtual Channel, and Single Function. Signed-off-by: Hans Zhang <hans.zhang@cixtech.com> [mani: moved the PCI ID definitions and squashed Kconfig change] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: sort Kconfig menu entry, squash https://lore.kernel.org/r/aSBqp0cglr-Sc8na@stanley.mountain] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251108140305.1120117-8-hans.zhang@cixtech.com 
Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based on the
Cadence High Performance Architecture (HPA) PCIe core.

The controller supports MSI/MSI-X via GICv3, Single Virtual Channel, and
Single Function.

Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
[mani: moved the PCI ID definitions and squashed Kconfig change]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: sort Kconfig menu entry, squash
https://lore.kernel.org/r/aSBqp0cglr-Sc8na@stanley.mountain]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20251108140305.1120117-8-hans.zhang@cixtech.com
PCI: cadence: Add module support for platform controller driver 2025-11-14T17:27:48+00:00 Manikandan K Pillai mpillai@cadence.com 2025-11-08T14:02:56+00:00 611627a4e5e4af7b96aab4f10d130f6a8a615020 Add support for building PCI cadence platforms as a module. Signed-off-by: Manikandan K Pillai <mpillai@cadence.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251108140305.1120117-2-hans.zhang@cixtech.com 
Add support for building PCI cadence platforms as a module.

Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20251108140305.1120117-2-hans.zhang@cixtech.com
PCI: sg2042: Add Sophgo SG2042 PCIe driver 2025-09-19T18:22:27+00:00 Chen Wang unicorn_wang@outlook.com 2025-09-12T02:36:31+00:00 1c72774df028429836eec3394212f2921bb830fc Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe controller in SG2042 works in host mode only, supporting data rate up to 16 GT/s and lanes up to x16 or x8. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> [mani: reworded description and minor code cleanups] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com 
Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses
the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe
controller in SG2042 works in host mode only, supporting data rate up to 16
GT/s and lanes up to x16 or x8.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
[mani: reworded description and minor code cleanups]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com
PCI: j721e: Fix host/endpoint dependencies 2025-06-02T21:02:37+00:00 Arnd Bergmann arnd@arndb.de 2025-04-23T16:25:16+00:00 3c05e88413f7b7145795dc1ad56983e75bca07a7 The j721e driver has a single platform driver that can be built-in or a loadable module, but it calls two separate backend drivers depending on whether it is a host or endpoint. If the two modes are not the same, we can end up with a situation where the built-in pci-j721e driver tries to call the modular host or endpoint driver, which causes a link failure: ld.lld-21: error: undefined symbol: cdns_pcie_ep_setup >>> referenced by pci-j721e.c >>> drivers/pci/controller/cadence/pci-j721e.o:(j721e_pcie_probe) in archive vmlinux.a ld.lld-21: error: undefined symbol: cdns_pcie_host_setup >>> referenced by pci-j721e.c >>> drivers/pci/controller/cadence/pci-j721e.o:(j721e_pcie_probe) in archive vmlinux.a Rework the dependencies so that the 'select' is done by the common Kconfig symbol, based on which of the two are enabled. Effectively this means that having one built-in makes the other either built-in or disabled, but all configurations will now build. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://patch.msgid.link/20250423162523.2060405-1-arnd@kernel.org 
The j721e driver has a single platform driver that can be built-in or a
loadable module, but it calls two separate backend drivers depending on
whether it is a host or endpoint.

If the two modes are not the same, we can end up with a situation where the
built-in pci-j721e driver tries to call the modular host or endpoint
driver, which causes a link failure:

  ld.lld-21: error: undefined symbol: cdns_pcie_ep_setup
  >>> referenced by pci-j721e.c
  >>>               drivers/pci/controller/cadence/pci-j721e.o:(j721e_pcie_probe) in archive vmlinux.a

  ld.lld-21: error: undefined symbol: cdns_pcie_host_setup
  >>> referenced by pci-j721e.c
  >>>               drivers/pci/controller/cadence/pci-j721e.o:(j721e_pcie_probe) in archive vmlinux.a

Rework the dependencies so that the 'select' is done by the common Kconfig
symbol, based on which of the two are enabled. Effectively this means that
having one built-in makes the other either built-in or disabled, but all
configurations will now build.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://patch.msgid.link/20250423162523.2060405-1-arnd@kernel.org
PCI: j721e: Add support to build as a loadable module 2025-06-02T21:02:37+00:00 Siddharth Vadapalli s-vadapalli@ti.com 2025-04-17T12:44:08+00:00 a2790bf81f0f7b0fb683204cd3bef07feecb9958 The 'pci-j721e.c' driver is the application/glue/wrapper driver for the Cadence PCIe Controllers on TI SoCs. Implement support for building it as a loadable module. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250417124408.2752248-5-s-vadapalli@ti.com 
The 'pci-j721e.c' driver is the application/glue/wrapper driver for the
Cadence PCIe Controllers on TI SoCs. Implement support for building it as a
loadable module.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250417124408.2752248-5-s-vadapalli@ti.com
PCI: cadence: Add support to build pcie-cadence library as a kernel module 2025-06-02T21:02:33+00:00 Kishon Vijay Abraham I kishon@ti.com 2025-04-17T12:44:05+00:00 f876904e44360449e64e2d38c428eba3a03d7a47 Currently, the Cadence PCIe controller driver can be built as a built-in module only. Since PCIe functionality is not a necessity for booting, add support to build the Cadence PCIe driver as a loadable module as well. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250417124408.2752248-2-s-vadapalli@ti.com 
Currently, the Cadence PCIe controller driver can be built as a built-in
module only. Since PCIe functionality is not a necessity for booting, add
support to build the Cadence PCIe driver as a loadable module as well.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250417124408.2752248-2-s-vadapalli@ti.com
PCI: Fix typos 2024-09-19T19:24:00+00:00 Bjorn Helgaas bhelgaas@google.com 2024-03-14T19:54:46+00:00 5c7bdac783be8dcba1427460e7971445f839a5e2 Fix typos. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 
Fix typos.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: j721e: Make TI J721E depend on ARCH_K3 2024-01-06T04:51:51+00:00 Peter Robinson pbrobinson@gmail.com 2024-01-04T21:39:06+00:00 177c9ac6ab3fa585608a16877b1fa1aad832571c The J721E PCIe is hardware specific to TI SoC parts so add a dependency on that so it's available for those SoC parts and for compile testing but not necessarily everyone who enables the Cadence PCIe controller. Link: https://lore.kernel.org/linux-pci/20240104213910.1426843-1-pbrobinson@gmail.com Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> 
The J721E PCIe is hardware specific to TI SoC parts so add a dependency
on that so it's available for those SoC parts and for compile testing but
not necessarily everyone who enables the Cadence PCIe controller.

Link: https://lore.kernel.org/linux-pci/20240104213910.1426843-1-pbrobinson@gmail.com
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
PCI: Use consistent controller Kconfig menu entry language 2023-04-20T21:18:04+00:00 Bjorn Helgaas bhelgaas@google.com 2023-04-18T17:43:33+00:00 80c170d7b13d0a46a46f869774baf3c02d775654 Use "PCIe controller" consistently instead of "host bridge", "bus driver", etc. Annotate with "(host mode)" or "(endpoint mode)" as needed. Link: https://lore.kernel.org/r/20230418174336.145585-5-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 
Use "PCIe controller" consistently instead of "host bridge", "bus driver",
etc.  Annotate with "(host mode)" or "(endpoint mode)" as needed.

Link: https://lore.kernel.org/r/20230418174336.145585-5-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: j721e: Add TI J721E PCIe driver 2020-08-03T13:49:55+00:00 Kishon Vijay Abraham I kishon@ti.com 2020-07-22T11:03:15+00:00 f3e25911a430ed16ec209929183df762fe9c785b Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports MSI and MSI-X support *) Supports upto GEN3 speed mode *) Supports SR-IOV capability *) Ability to route all transactions via SMMU (support will be added in a later patch). Link: https://lore.kernel.org/r/20200722110317.4744-14-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 
Add support for PCIe controller in J721E SoC. The controller uses the
Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller
will work in both host mode and device mode.
Some of the features of the controller are:
  *) Supports both RC mode and EP mode
  *) Supports MSI and MSI-X support
  *) Supports upto GEN3 speed mode
  *) Supports SR-IOV capability
  *) Ability to route all transactions via SMMU (support will be added
     in a later patch).

Link: https://lore.kernel.org/r/20200722110317.4744-14-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>